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| ksz8873mll/fll/rll integrated 3 - port 10/100 managed switch with phys revision 1.6 linkmd is a registered trademark of micrel, inc. product names used in this datasheet are for identification purposes only and may be trademarks of their respective companies . micrel inc. ? 2180 fortune drive ? san jose, ca 95131 ? usa ? tel +1 (408) 944 - 0800 ? fax + 1 (408) 474 - 1000 ? http://www.micrel.com september 20, 2013 revision 1 .6 general description the ksz8873mll /fll/rll are highly - integrated 3 - port switch es on a chip ics in the industrys smallest footprint. they are designed to enable a new generation of low port count, cost - sensitive, and power - efficient 10/100mbps switch systems. low power consumption, advanced power management and sophisticated qos features (e.g., ipv6 priori ty classification support) make these devices ideal for iptv, ip - stb, voip, automotive, and industrial applications. the ksz8873 family is designed to support the green requirement in todays switch systems. advanced power management schemes include hardware power down, software power down, per port power down and the energy detect mode that shuts downs the transceiver when a port is idle. ksz8873mll/fll/rll also offers a by - pass mode . in this mode, the processor connected to the switch through the mii inte rface can be shut down without impacting the normal switch operation. the configurations provided by the ksz8873 family enables the flexibility to meet requirements of different applications: ? ksz8873mll: two 10/100base - t/tx transceivers and one mii int erface. ? ksz8873rll: two 10/100base - t/tx transceivers and one rmii interface. ? ksz8873fll: two 100base - fx transceivers and one mii interface. the device is available in rohs - compliant 64 - pin lqfp package. industrial - grade and qualified aec - q100 automotive -g rade v ersion are also available (see ordering information section) datasheets and support documentation are available on micrels web site at: www.micrel.com . functional diagram downloaded from: http:///
micrel, inc. ksz8873mll/fll/rll september 20, 2013 2 revision 1.6 features advanced switch features ? ieee 802.1q vlan support for up to 16 groups (full - range of vlan ids) ? vlan id tag/untag options, per port basis ? ieee 802.1p/q tag insertion or removal on a per port basis (egress) ? programmable rate limiting at the ingress and egress on a per port basis ? broadcast storm protection with % control (global and per port basis) ? ieee 802.1d rapid spanning tree protocol support ? tail tag mode (1 byte added before fcs) support at port3 to inform the processor which ingress port receives the packet and its priority ? bypass feature which automatically sustain s the switch function between port1 and port2 when cpu (port 3 interface) goes to the sleep mode ? self - address f iltering ? individual mac address for port1 and port2 ? s upport rmii interface and 50 m h z reference clock output ? mac mii interface supports both mac mode and phy mode ? igmp snooping (ipv4) support for multicast packet filtering ? ipv4/ipv6 qo s support . ? mac filtering function to forward unknown unicast packets to specified port comprehensive configuration register access ? serial management interface (smi) to all internal registers ? mii management (miim) interface to phy registers ? high speed spi and i 2 c interface to all internal registers ? i/0 pins strapping and eeprom to program selective registers in unmanaged switch mode ? control registers configurable on the fly (port - priority, 802.1p/d/q, an) qos/cos packet prioritization support ? p er port, 802.1p and diffserv - based ? re- mapping of 802.1p priority field per port basis four priority levels proven integrated 3 - port 10/100 ethernet switch ? 3rd generation switch with three macs and two ? phys fully compliant with ieee 802.3u standard ? non - bl ocking switch fabric assures fast packet delivery by utilizing an 1k mac address lookup table and a store - and - forward architecture ? full duplex ieee 802.3x flow control (pause) with force mode option ? half - duplex back pressure flow control ? hp auto mdi - x f or reliable detection of and correction for straight - through and crossover cables with disable and enable option ? micrel linkmd ? tdr - based cable diagnostics permit identification of faulty copper cabling on port 2 ? comprehensive led indicator support for lin k, activity, full/half duplex and 10/100 speed ? hbm esd rating 3 kv switch monitoring features ? port mirroring/monitoring/sniffing: ingress and/or egress traffic to any port or mii ? mib counters for fully compliant statistics gathering 34 mib counters per por t ? loopback modes for remote diagnostic of failure low power dissipation: ? full - chip hardware power - down (register configuration not saved) ? full - chip software power - down (register configuration not saved) ? energy - detect mode support ? dynamic clock tree shutdown feature ? per port based software power - save on phy (idle link detection, register configuration preserved) ? voltages: single 3.3v supply with internal 1.8v ldo for 3.3v vddio ? optional 3.3v, 2.5v and 1.8v for vddio ? transceiver power 3.3v for vdda_3. 3 industrial temperature range: C 40 c to +85 c available in 64 - pin l qfp, lead -f ree package applications ? voip phone ? set - top/game box ? automotive ethernet ? industrial control ? iptv pof ? soho residential gateway ? broadband gateway/firewall/vpn ? integrated dsl/cable modem ? wireless lan access point + gateway ? standalone 10/100 switch downloaded from: http:/// micrel, inc. ksz8873mll/fll/rll september 20, 2013 3 revision 1.6 ordering information part number temperature range package lead finish/grade ksz8873 m ll 0 c to 70 c 64 -pin l qfp pb- free/commercial ksz8873 m lli C 40 c to +85 c 64 -pin l qfp pb- free/industrial ksz887 3mll am C 40 c to +85 c 64 -pin l qfp pb- free/ automotive grade 3 ksz8873fll 0 c to 70 c 64 -pin l qfp pb- free/commercial ksz8873flli C 40 c to +85 c 64 -pin l qfp pb- free/industrial ksz8873 r ll 0 c to 70 c 64 -pin l qfp pb- free/commercial ksz8873 r lli C 40 c to +85 c 64 -pin l qfp pb- free/industrial ksz8873 r ll u C 40 c to +85 c 64 -pin l qfp pb- free/ automotive grade 3 revision history revision date summary of changes 1.0 03/25/08 initial release 1.1 06/26/09 combined register description to initial release. 1.2 09/08/09 remove d linkmd feature. update d the electrical characteristics. 09/23/09 add ed linkmd feature on port 2. fix ed the typo on r egister 194 10/01/09 modified p in 31(smrxd31) description. 1.3 08/1 0/10 removed turbo mii feature and its timing, add mdc/mdio timing, update the descriptions of the by - pass mode, tag insertion, power management, pins , registers , and so on. update max rating , rmii timing and electrical characteristics . 1. 4 05/ 25 /11 update d r egister 6 with strap pins description, junction thermal and so on. added the descriptions of the registers from r egister s 175 - 186. added a note for port register control 12, updated the description for some registers, updated reset timing diagram. 1. 5 07/ 2 8/11 update d description for mdc/mdio smi mode and igmp mode. esd rating updated to 3kv. update data of lead temperature. 11/01/11 correct typo error in ordering information table. 11/15/11 correct typo error for mdi - x status in the phy r egister 31. 1. 6 04 / 11 /1 3 add or update the notes for p in scrs3 description, the port register control 0 bit 2 and the port register control 5 bit 7. update the operation voltage min/max for different vddio. update the pin d escription for p in 30 and p in 33. change ttl i/o to cmos i/o. update the r egister 166 description and the default value. add ksz8873rllu automotive device in order information table. add a note for register 195 bits [ 5:4]. downloaded from: http:/// micrel, inc. ksz8873mll/fll/rll september 20, 2013 4 revision 1.6 contents general description ................................................................................................................................................................ 1 functional diagram ................................................................................................................................................................ . 1 features .................................................................................................................................................................................. 2 ordering information ............................................................................................................................................................... 3 revision history ...................................................................................................................................................................... 3 contents .................................................................................................................................................................................. 4 list of figures ........................................................................................................................................................................ 10 list of tables ......................................................................................................................................................................... 11 pin configuration ................................................................................................................................................................... 12 pin description and i/o assignment ..................................................................................................................................... 13 functional description ........................................................................................................................................................... 19 functional overview: physical layer transceiver ................................................................................................................ 19 100base - tx transmit ...................................................................................................................................................... 19 pll clock synthesizer ...................................................................................................................................................... 19 scrambler/de - scrambler (100base - tx only) .................................................................................................................. 19 100base - fx operation .................................................................................................................................................... 20 100base - fx signal detection .......................................................................................................................................... 20 100base - fx far - end fault .............................................................................................................................................. 20 10base - t transmit ........................................................................................................................................................... 20 10base - t receive ............................................................................................................................................................ 20 mdi/mdi - x auto crossover ............................................................................................................................................... 20 straight cable ................................................................................................................................................................ 21 crossover cable ............................................................................................................................................................ 22 auto - negotia tion ................................................................................................................................................................ 23 linkmd ? cable diagnostics ............................................................................................................................................... 24 access ............................................................................................................................................................................ 24 usage ............................................................................................................................................................................. 24 functional overview: power management ........................................................................................................................... 25 normal operation mode .................................................................................................................................................... 25 energy - detect mode .......................................................................................................................................................... 25 soft power - down mode ..................................................................................................................................................... 26 power - sa ving mode .......................................................................................................................................................... 26 port - based power - down mode ......................................................................................................................................... 26 hardware power down ...................................................................................................................................................... 26 functional overview: mac and switch ................................................................................................................................ . 27 address lookup ................................................................................................................................................................ . 27 learning ............................................................................................................................................................................. 27 migration ............................................................................................................................................................................ 27 aging .................................................................................................................................................................................. 27 forwarding ......................................................................................................................................................................... 27 switching engine ............................................................................................................................................................... 30 mac operatio n .................................................................................................................................................................. 30 inter packet gap (ipg) .................................................................................................................................................. 30 back - off algorithm ......................................................................................................................................................... 30 late collision ................................................................................................................................................................ . 30 illegal frames ................................................................................................................................................................ 30 full duplex fl ow control ................................................................................................................................................ 30 half - duplex backpressure ............................................................................................................................................. 30 broadcast storm protection ........................................................................................................................................... 31 port individual mac address and source port filtering ................................................................................................ 31 mii interface operation ...................................................................................................................................................... 31 rmii interface operation ................................................................................................................................................... 32 mii management (miim) interface ..................................................................................................................................... 34 serial management interface (smi) .................................................................................................................................. 35 downloaded from: http:/// micrel, inc. ksz8873mll/fll/rll september 20, 2013 5 revision 1.6 advanced switch functions .................................................................................................................................................. 36 by pass mode ..................................................................................................................................................................... 36 ieee 802.1q vlan support .............................................................................................................................................. 36 qos priority support .......................................................................................................................................................... 37 port - based priority ............................................................................................................................................................ 37 802.1p - based priority ........................................................................................................................................................ 37 diffse rv - based priority ................................................................................................................................................... 38 spanning tree support ..................................................................................................................................................... 38 rapid spanning tree support ........................................................................................................................................... 39 tail tagging mode ............................................................................................................................................................. 39 igmp suppo rt .................................................................................................................................................................... 40 igmp snooping .............................................................................................................................................................. 40 igmp send - back to the subscribed port ...................................................................................................................... 40 port mirroring support ....................................................................................................................................................... 40 rate limiting support ........................................................................................................................................................ 41 unicas t mac address filtering .......................................................................................................................................... 41 configuration interface ...................................................................................................................................................... 41 i 2 c master serial bus configuration .............................................................................................................................. 41 i 2 c slave serial bus configuration ................................................................................................................................ 42 spi slave serial bus configuration ............................................................................................................................... 43 loopback support ............................................................................................................................................................. 46 far - end loopback ......................................................................................................................................................... 46 near - end (remote) loopback ....................................................................................................................................... 47 mii management (miim) registers ........................................................................................................................................ 48 phy1 register 0 (phyad = 0x1, regad = 0x0): mii basic control ................................................................................ 49 phy2 register 0 (phyad = 0x2, regad = 0x0): mii basic contro l ................................................................................ 49 phy1 register 1 (phyad = 0x1, regad = 0x1): mii basic status ................................................................................. 50 phy2 register 1 (phyad = 0x2, regad = 0x1): mii basic status ................................................................................. 50 phy1 register 2 (phyad = 0x1, regad = 0x2): phyid high ........................................................................................ 50 phy2 register 2 (phyad = 0x2, regad = 0x2): phyid high ........................................................................................ 50 phy1 register 3 (phyad = 0x1, regad = 0x3): ph yid low ........................................................................................ 50 phy2 register 3 (phyad = 0x2, regad = 0x3): phyid low ........................................................................................ 50 phy1 register 4 (phyad = 0x1, regad = 0x4): auto - negotiation advertisement ability ............................................. 51 phy2 register 4 (phyad = 0x2, regad = 0x4): auto - negotiation advertisement ability ............................................. 51 phy1 register 5 (phyad = 0x1, regad = 0x5): auto - negotiation link partner ability ................................................. 51 phy2 register 5 (phyad = 0x2, regad = 0x5): auto - negotiation link partner ability ................................................. 51 phy1 register 29 (phyad = 0x1, regad = 0x1d): not supported ................................................................................ 52 phy2 register 29 (phyad = 0x2, regad = 0x1d): linkmd control/status .................................................................. 52 phy1 register 31 (phyad = 0x1, regad = 0x1f): phy special control/status ........................................................... 52 phy2 register 31 (phyad = 0x2, regad = 0x1f): phy special control/status ........................................................... 52 memory map (8 - bit registers) .............................................................................................................................................. 53 global registers ................................................................................................................................................................ 53 p ort registers .................................................................................................................................................................... 53 advanced control registers .............................................................................................................................................. 53 downloaded from: http:/// micrel, inc. ksz8873mll/fll/rll september 20, 2013 6 revision 1.6 r egister description .............................................................................................................................................................. 54 global registers (registers 0 C 15) .................................................................................................................................. 54 register 0 (0x00): chip id0 ........................................................................................................................................... 54 register 1 (0x01): chip id1 / start switch ..................................................................................................................... 54 register 2 (0x02): global control 0 ............................................................................................................................... 54 register 3 (0x03): global control 1 ............................................................................................................................... 55 register 4 (0x04): global control 2 ............................................................................................................................... 55 register 5 (0x05): global control 3 ............................................................................................................................... 56 register 6 (0x06): global control 4 ............................................................................................................................... 57 register 7 (0x07): global control 5 ............................................................................................................................... 57 register 8 (0x08): global control 6 ............................................................................................................................... 58 register 9 (0x09): global control 7 ............................................................................................................................... 58 register 10 (0x0a): global control 8 ............................................................................................................................. 58 register 11 (0x0b): global control 9 ............................................................................................................................. 58 register 12 (0x0c): global control 10 ........................................................................................................................... 58 register 13 (0x0d): global control 11 ........................................................................................................................... 59 register 14 (0x0e): global control 12 ........................................................................................................................... 59 register 15 (0x0f): global control 13 ........................................................................................................................... 60 port registers (registers 16 C 95) .................................................................................................................................... 60 register 16 (0x10): port 1 control 0 .............................................................................................................................. 60 register 32 (0x20): port 2 control 0 .............................................................................................................................. 60 register 48 (0x30): port 3 control 0 .............................................................................................................................. 60 register 17 (0x11): port 1 control 1 .............................................................................................................................. 62 register 33 (0x21): port 2 control 1 .............................................................................................................................. 62 register 49 (0x31): port 3 control 1 .............................................................................................................................. 62 register 18 (0x12): port 1 control 2 .............................................................................................................................. 62 register 34 (0x22): port 2 control 2 .............................................................................................................................. 62 register 50 (0x32): port 3 control 2 .............................................................................................................................. 62 register 19 (5) (0x13): port 1 control 3 ........................................................................................................................... 64 register 35 (0x23): port 2 control 3 .............................................................................................................................. 64 register 51 (0x33): port 3 control 3 .............................................................................................................................. 64 register 20 (5) (0x14): port 1 control 4 ........................................................................................................................... 64 register 36 (0x24): port 2 control 4 .............................................................................................................................. 64 register 52 (0x34): port 3 control 4 .............................................................................................................................. 64 register 21 (0x15): port 1 control 5 .............................................................................................................................. 64 register 37 (0x25): port 2 control 5 .............................................................................................................................. 64 register 53 (0x35): port 3 control 5 .............................................................................................................................. 64 register 22[6:0] (0x16): port 1 q0 ingress data rate limit .......................................................................................... 65 register 38[6:0] (0x26): port 2 q0 ingress data rate limit .......................................................................................... 65 register 54[6:0] (0x36): port 3 q0 ingress data rate limit .......................................................................................... 65 register 23[6:0] (0x17): port 1 q1 ingress data rate limit .......................................................................................... 66 register 39[6:0] (0x27): port 2 q1 ingress data rate limit .......................................................................................... 66 register 55[6:0] (0x37): port 3 q1 ingress data rate limit .......................................................................................... 66 register 24[6:0] (0x18): port 1 q2 ingress data rate limit .......................................................................................... 66 register 40[6:0] (0x28): port 2 q2 ingress data rate limit .......................................................................................... 66 register 56[6:0] (0x38): port 3 q2 ingress data rate limit .......................................................................................... 66 register 25[6:0] (0x19): port 1 q3 ingress data rate limit .......................................................................................... 66 register 41[6:0] (0x29): port 2 q3 ingress data rate limit .......................................................................................... 66 register 57[6:0] (0x39): port 3 q3 ingress data rate limit .......................................................................................... 66 register 26 (0x1a): port 1 phy special control/status ................................................................................................ 68 register 42 (0x2a): port 2 phy special control/status ................................................................................................ 68 register 58 (0x3a): reserved, not applied to port 3 .................................................................................................... 68 register 27 (0x1b): port 1 not support ......................................................................................................................... 68 register 43 (0x2b): linkmd result ............................................................................................................................... 68 register 59 (0x3b): reserved, not applied to port 3 .................................................................................................... 68 register 28 (0x1c): port 1 control 12 ........................................................................................................................... 69 register 44 (0x2c): port 2 control 12 ........................................................................................................................... 69 downloaded from: http:/// micrel, inc. ksz8873mll/fll/rll september 20, 2013 7 revision 1.6 register 60 (0x3c): reserved, not applied to port 3 .................................................................................................... 69 register 29 (0x1d): port 1 control 13 ........................................................................................................................... 70 register 45 (0x2d): port 2 control 13 ........................................................................................................................... 70 register 61 (0x3d): reserved, not applied to port 3 .................................................................................................... 70 register 30 (0x1e): port 1 status 0 ............................................................................................................................... 71 register 46 (0x2e): port 2 status 0 ............................................................................................................................... 71 register 62 (0x3e): reserved, not applied to port 3 .................................................................................................... 71 register 31 (0x1f): port 1 status 1 ............................................................................................................................... 72 register 47 (0x2f): port 2 status 1 ............................................................................................................................... 72 register 63 (0x3f): port 3 status 1 ............................................................................................................................... 72 register 67 (0x43): reset .............................................................................................................................................. 72 advanced control registers (registers 96 -1 98 ) ............................................................................................................... 73 register 96 (0x60): tos priority control register 0 ..................................................................................................... 73 register 97 (0x61): tos priority control register 1 ..................................................................................................... 73 register 98 (0x62): tos priority control reg ister 2 ..................................................................................................... 73 register 99 (0x63): tos priority control register 3 ..................................................................................................... 74 register 100 (0x64): tos priority control register 4 ................................................................................................... 74 register 101 (0x65): tos priority control register 5 ................................................................................................... 74 register 102 (0x66): tos priority control register 6 ................................................................................................... 75 register 103 (0x67): tos priority control register 7 ................................................................................................... 75 register 104 (0x68): tos priority control register 8 ................................................................................................... 75 register 105 (0x69): tos priority control register 9 ................................................................................................... 76 register 106 (0x6a): tos priority control register 10 ................................................................................................ . 76 register 107 (0x6b): tos priority control register 11 ................................................................................................ . 76 register 108 (0x6c): tos priority control register 12 ................................................................................................ . 77 register 109 (0x6d): tos priority control register 13 ................................................................................................ . 77 register 110 (0x6e): tos priority control register 14 ................................................................................................ . 77 register 111 (0x6f): tos priority control register 15 ................................................................................................ . 78 registers 112 to 117 ......................................................................................................................................................... 78 register 112 (0x70): mac address register 0 ................................................................................................................. 78 register 113 (0x71): mac address register 1 .............................................................................................................. 78 register 114 (0x72): mac address register 2 .............................................................................................................. 78 register 115 (0x73): mac address register 3 .............................................................................................................. 78 register 116 (0x74): mac address register 4 .............................................................................................................. 78 register 117 (0x75): mac address register 5 .............................................................................................................. 78 registers 118 to 120 ......................................................................................................................................................... 79 register 118 (0x76): user defined register 1 ............................................................................................................... 79 register 119 (0x77): user defined register 2 ............................................................................................................... 79 register 120 (0x78): user defined register 3 ............................................................................................................... 79 registers 121 to 131 ......................................................................................................................................................... 79 register 121 (0x79): indirect access control 0 ............................................................................................................. 79 register 122 (0x7a): indirect access control 1 ............................................................................................................. 79 register 123 (0x7b): indirect data register 8 ............................................................................................................... 80 register 124 (0x7c): indirect data register 7 ............................................................................................................... 80 register 125 (0x7d): indirect data register 6 ............................................................................................................... 80 register 126 (0x7e): indirect data register 5 ............................................................................................................... 80 register 127 (0x7f): indirect data register 4 ............................................................................................................... 80 register 128 (0x80): indirect data register 3 ............................................................................................................... 80 register 129 (0x81): indirect data register 2 ............................................................................................................... 80 register 130 (0x82): indirect data register 1 ............................................................................................................... 81 register 131 (0x83): indirect data register 0 ............................................................................................................... 81 register 147~142(0x93~0x8e): station mac address 1 maca1 ................................................................................. 81 register 153~148 (0x99~0x94): station mac address 2 maca2 ................................................................................ 81 register 154[6:0] (0x9a): port 1 q0 egress data rate limit ........................................................................................ 81 register 158[6:0] (0x9e): port 2 q0 egress data rate limit ........................................................................................ 81 register 162[6:0] (0xa2): port 3 q0 egress data rate limit ........................................................................................ 81 register 155[6:0] (0x9b): port 1 q1 egress data rate limit ........................................................................................ 81 downloaded from: http:/// micrel, inc. ksz8873mll/fll/rll september 20, 2013 8 revision 1.6 register 159[6:0] (0x9f): port 2 q1 egress data rate limit ........................................................................................ 81 register 163[6:0] (0xa3): port 3 q1 egress data rate limit ........................................................................................ 81 register 156[6:0] (0x9c): port 1 q2 egress data rate limit ........................................................................................ 82 register 160[6:0] (0xa0): port 2 q2 egress data rate limit ........................................................................................ 82 register 164[6:0] (0xa4): port 3 q2 egress data rate limit ........................................................................................ 82 register 157[6:0] (0x9d): port 1 q3 egress data rate limit ........................................................................................ 82 register 161[6:0] (0xa1): port 2 q3 egress data rate limit ........................................................................................ 82 register 165[6:0] (0xa5): port 3 q3 egress data rate limit ........................................................................................ 82 register 166 (0xa6): ksz8873 mode indicator ............................................................................................................. 82 register 167 (0xa7): high - priority packet buffer reserved for q3 ............................................................................... 82 register 168 (0xa8): high - priority packet buffer reserved for q2 ............................................................................... 82 register 169 (0xa9): high - priority packet buffer reserved for q1 ............................................................................... 83 register 170 (0xaa): high - priority packet buffer reserved for q0 .............................................................................. 83 register 171 (0xab): pm usage flow control select mode 1 ...................................................................................... 83 register 172 (0xac): pm usage flow control select mode 2 ...................................................................................... 83 register 173 (0xad): pm usage flow control select mode 3 ...................................................................................... 83 register 174 (0xae): pm usage flow control select mode 4 ...................................................................................... 83 register 175 (0xaf): txq split for q3 in port 1 ............................................................................................................ 84 register 176 (0xb0): txq split for q2 in port 1 ............................................................................................................ 84 register 177 (0xb1): txq split for q1 in port 1 ............................................................................................................ 84 register 178 (0xb2): txq split for q0 in port 1 ............................................................................................................ 84 register 179 (0xb3): txq split for q3 in port 2 ............................................................................................................ 85 register 180 (0xb4): txq split for q2 in port 2 ............................................................................................................ 85 register 181 (0xb5): txq split for q1 in port 2 ............................................................................................................ 85 register 182 (0xb6): txq split for q0 in port 2 ............................................................................................................ 85 register 183 (0xb7): txq split for q3 port 3 ................................................................................................................ 86 register 184 (0xb8): txq split for q2 port 3 ................................................................................................................ 86 register 185 (0xb9): txq split for q1 in port 3 ............................................................................................................ 86 register 186 (0xba): txq split for q0 in port 3 ............................................................................................................ 86 register 187 (0xbb): interrupt enable register ............................................................................................................ 86 register 188 (0xbc): link change interrupt .................................................................................................................. 87 register 189 (0xbd): force pause off iteration limit enable ....................................................................................... 87 register 192 (0xc0): fiber signal threshold ................................................................................................................ 87 register 19 3 (0xc 1 ): internal 1.8v ldo control ........................................................................................................... 87 register 194 (0xc2): insert src pvid .......................................................................................................................... 88 register 195 (0xc3): power management and led mode ........................................................................................... 89 register 196(0xc4): sleep mode .................................................................................................................................. 90 register 198 (0xc6): forward invalid vid frame and host mode ................................................................................ 90 static mac address table .................................................................................................................................................... 91 vlan table ........................................................................................................................................................................... 93 dynamic mac address table ............................................................................................................................................... 94 management information base (m ib) counters ................................................................................................................... 95 additional mib counter information ............................................................................................................................... 98 absolute maximum ratings .................................................................................................................................................. 99 operating ratings ................................................................................................................................................................ . 99 electrical characteristics ....................................................................................................................................................... 99 timing specifications .......................................................................................................................................................... 101 eeprom timing ............................................................................................................................................................. 101 mii timing ........................................................................................................................................................................ 102 rmii timing ..................................................................................................................................................................... 104 i 2 c slave mode t iming .................................................................................................................................................... 105 spi timing ....................................................................................................................................................................... 107 auto - negotiation timing .................................................................................................................................................. 109 mdc/mdio timing .......................................................................................................................................................... 110 reset timing .................................................................................................................................................................... 111 reset circuit .................................................................................................................................................................... 112 downloaded from: http:/// micrel, inc. ksz8873mll/fll/rll september 20, 2013 9 revision 1.6 selection of isolation transformers ..................................................................................................................................... 113 selection of reference crystal ............................................................................................................................................ 113 package information and recommended landing pattern ................................................................................................ 114 downloaded from: http:/// micrel, inc. ksz8873mll/fll/rll september 20, 2013 10 revision 1.6 list of figures figure 1. typical straight cable connection ........................................................................................................................ 21 figure 2. typical crossover cable connection .................................................................................................................... 22 figure 3. auto - negotiation and parallel operation ............................................................................................................... 23 figure 4. destination addres s lookup flow chart ? stage 1 ............................................................................................... 28 figure 5. destination address resolution flow chart ? stage 2 .......................................................................................... 29 figure 6. 802.1p priority field format .................................................................................................................................. 37 figure 7. tail tag frame format .......................................................................................................................................... 39 figure 8. eeprom configuration timing diagram .............................................................................................................. 42 figure 9. spi write data cycle ............................................................................................................................................. 44 figure 10. spi read data cycle ........................................................................................................................................... 44 figure 11. spi multiple write ................................................................................................................................................ 45 figure 12. spi multiple read ................................................................................................................................................ 45 figure 13. far - end loopback path ....................................................................................................................................... 46 figure 14. near - end (remote) loopback path .................................................................................................................... 47 figure 15. eeprom interface input timing diagram ......................................................................................................... 101 figure 16. eeprom interface output timing diagram ...................................................................................................... 101 figure 17. mac mode mii timing ? data received from mii ............................................................................................. 102 figure 18. mac mode mii timing ? data transmitted to mii ............................................................................................. 102 figure 19. phy mode mii timing ? data received from mii .............................................................................................. 103 figure 20. phy mode mii timing ? data transmitted to mii .............................................................................................. 103 figure 21. rmii timing ? data received from rmii ........................................................................................................... 104 figure 22. rmii timing parameters .................................................................................................................................... 104 figure 23. i 2 c input timing ................................................................................................................................................. 105 figure 24. i 2 c start bit timing ............................................................................................................................................ 105 figure 25. i 2 c stop bit timing ............................................................................................................................................. 105 figure 26. i 2 c output timing .............................................................................................................................................. 105 figure 27. spi input timing ................................................................................................................................................ 107 figure 28. spi output timing .............................................................................................................................................. 108 figure 29. auto - negotiation timing .................................................................................................................................... 109 figure 30. mdc/mdio timing ............................................................................................................................................. 110 figure 31. reset timing ...................................................................................................................................................... 111 figure 32. recommended reset circuit ............................................................................................................................. 112 figure 33. recommended reset circuit for interfacing with cpu/fpga reset output .................................................... 112 downloaded from: http:/// micrel, inc. ksz8873mll/fll/rll september 20, 2013 11 revision 1.6 list of tables table 1. fx signal threshold ................................................................................................................................................ 20 table 2. mdi/mdi - x pin definitions ...................................................................................................................................... 21 table 3. internal function block status ................................................................................................................................ 25 table 4. mii signals .............................................................................................................................................................. 32 table 5. rmii clock setting .................................................................................................................................................. 33 table 6. rmii signal description ........................................................................................................................................... 33 table 7. rmii signal connections ......................................................................................................................................... 34 table 8. mii management interface frame format .............................................................................................................. 35 table 9. serial management interface (smi) frame format ................................................................................................ 35 table 10. fid + da lookup in vlan mode .......................................................................................................................... 36 table 11. fid + sa lookup in vlan mode .......................................................................................................................... 36 table 12. spanning tree states ........................................................................................................................................... 38 table 13. tail tag rules ....................................................................................................................................................... 40 table 14. spi connections ................................................................................................................................................... 44 ta ble 15. data rate limit table ........................................................................................................................................... 67 table 16. format of static mac table (8 entries) ................................................................................................................ 91 table 17. format of static vlan table (16 entries) ............................................................................................................. 93 table 18. format of dynamic mac address table (1k entries) .......................................................................................... 94 table 19. format of per port mib c ounters ....................................................................................................................... 95 table 20. port 1s per port mib counters indirect memory offsets ................................................................................... 96 table 21. format of all port dropped packet mib counters .............................................................................................. 97 table 22. all port dropped packet mib counters .............................................................................................................. 97 table 23. eeprom timing parameters ............................................................................................................................. 101 table 24. mac mode mii timing parameters ..................................................................................................................... 102 table 25. phy mode mii timing parameters ..................................................................................................................... 103 table 26. rmii timing parameters ..................................................................................................................................... 104 table 27. i 2 c timing parameters ........................................................................................................................................ 106 table 28. spi input timing parameters .............................................................................................................................. 107 table 29. spi output timing parameters ........................................................................................................................... 108 table 30. auto - negotiation timing parameters .................................................................................................................. 109 table 31. mdc/mdio timing parameters .......................................................................................................................... 110 table 32. reset timing parameters ................................................................................................................................... 111 table 33. transformer selection criteria ............................................................................................................................ 113 table 34. qualified single - port magnetics .......................................................................................................................... 113 table 35. typical reference crystal characteristics .......................................................................................................... 113 downloaded from: http:/// micrel, inc. ksz8873mll/fll/rll september 20, 2013 12 revision 1.6 pin configuration 64 - pin lqfp ( top view ) downloaded from: http:/// micrel, inc. ksz8873mll/fll/rll september 20, 2013 13 revision 1.6 pin description and i/o assignment pin number pin name type (1) description 1 rxm 1 i/o physical receive or transmit signal ( C differential) 2 rxp 1 i/o physical receive or transmit signal (+ differential) 3 a gnd gnd analog ground 4 txm1 i/o physical transmit or receive signal ( C differential) 5 txp 1 i/o physical transmit or receive signal (+ differential) 6 vdda _3.3 p 3.3v analog v dd 7 a gnd gnd analog ground. 8 iset o set physical transmit output current. pull- down this pin with an 11.8 k 1% resistor to ground. 9 vdd a_1.8 p 1.8 v analog core power input from vddco ( p in 56 ). 10 rxm 2 i/o physical receive or transmit signal ( C differential) 11 rxp 2 i/o physical receive or transmit signal (+ differential) 12 a gnd gnd analog ground. 13 txm2 i/o physical transmit or receive signal ( C differential) 14 txp 2 i/o physical transmit or receive signal (+ differential) 15 fxsd 2 i mll/rll: connect to analog ground by pull - down resistor . fll: fiber signal detect / factory test pin 16 pwrnd ipu chip power down input (active low). 17 x1 i 25 mhz or 50mhz crystal/oscillator clock connections. pins (x1, x2) connect to a crystal. if an oscillator is used, x1 connects to a 3.3v tolerant oscillator and x2 is a no connect. note: clock is 50ppm for crystal and oscil lator, the clock should be applied to x1 pin before reset voltage goes high. 18 x2 o 19 smtxen 3 i pu switch mii transmit enable 20 smtxd3 3/ en_refclko_3 lpu/ i mll/fll: switch mii transmit data bit 3 rll: strap option : rmii mode clock selection pu = enable refclko_3 output pd = disable refclko_3 output 21 smtxd 32/ nc i pu mll/fll: switch mii transmit data bit 2 rll: no connection 22 smtxd 31 i pu switch mii /rmii transmit data bit 1 23 smtxd 30 i pu switch mii /rmii transmit data bit 0 24 gnd gnd digital ground 25 vddio p 3.3v, 2.5v or 1.8v digital vdd input power supply for io with well decoupling capacitors. downloaded from: http:/// micrel, inc. ksz8873mll/fll/rll september 20, 2013 14 revision 1.6 pin description and i/o assignment (continued) pin number pin name type (1) description 26 smtxc 3/ refclki_3 i/o mll/fll: switch mii transmit clock (mii modes only) output in phy mii mode and sni mode input in mac mii and rmii mode. rll: reference clock input note: pull - down by resistor is needed if internal reference clock is used in rll by register 198 bit 3 . 27 smtxer 3/ mii_link_ 3 i pd switch mii transmit error in mii mode 0= mii link indicator from host in mii phy mode. 1= no link on port 3 mii phy mode and enable by - pass mode. 28 smrxdv 3 lpu/ o switch mii receive data valid strap option : mii mode selection pu = phy mode. pd = mac mode (in mac mode, port 3 mii has to connect a powered active external phy for the normal operation ) 29 smrxd3 3/ refclko_3 lpu/ o mll/fll: switch mii receive data bit 3 rll: ou t put reference clock in rmii mode. strap option : enable auto - negotiation on port 2 (p2anen) pu = en able p2anen pd = disable p2anen 30 smrxd 32 ip u /o switch mii receive data bit 2 strap option : force the speed on port 2 pu = force port 2 to 100bt if p2anen = 0 pd = force port 2 to 10bt if p2anen = 0 31 smrxd 31 ip u /o switch mii /rmii receive data bit 1 strap option : force duplex mode (p2dpx) pu = port 2 default to full duplex mode if p2anen = 1 and auto - negotiation fails. force port 2 in full duplex mode if p2anen = 0 . pd = p ort 2 set to half duplex mode if p2anen = 1 and auto - negotiation fails. force port 2 in half duplex mode if p2anen = 0. 32 gnd gnd digital ground 33 smrxd 30 lpu /o switch mii /rmii receive data bit 0 strap option : force flow control on port 2 (p2ffc) pu = always enable (force) port 2 flow control feature, regardless of a uto - n egotiation result. pd = port 2 flow control is enabled by auto - negotiation result. 34 scrs 3/ nc i pu /o mll/fll: switch mii carrier sense rll: no connection, internal pull up. note: for mll/fll part, when chip is configured as mac mode, this pin should be driven from crs pin of phy or from crs pin of fpga with a logic of ( txen | rxdv). if only full duplex is used, then this pin should be pull - down by 1k resister . downloaded from: http:/// micrel, inc. ksz8873mll/fll/rll september 20, 2013 15 revision 1.6 pin description and i/o assignment (continued) pin number pin name type (1) description 35 scol 3/ nc i pu /o mll/fll: switch mii collision detect rll: no connection, internal pull up. 36 smrxc 3/ nc i/o mll/fll: switch mii receive clock. output in phy mii mode input in mac mii mode rll: no connection. 37 gnd gnd digital ground 38 vddc p 1.8 v digital core power input from vddco ( p in 56). 39 spiq lpu/ o spi slave mode: serial data output note: an external pull - up is needed on this pin when it is in use. strap option: xclk frequency selection pu = 25 mhz pd = 50 mhz 40 spisn i pu spi slave mode: chip select (active low) when spisn is high, the ksz8873mll/fll/rll is deselected and spiq is held in high impedance state. a high - to - low transition is used to initiate spi data transfer. note: an external pull - up is needed on this pin when it is in use. 41 intrn opu interrupt active low signal to host cpu to indicate an interrupt status bit is set when lost link. refer to r egister 187 and 188. 42 scl _mdc i/o spi slave mode / i 2 c slave mode: clock input i 2 c master mode: clock output miim clock input 43 sda _mdio i pu /o spi slave mode: serial data input i 2 c master/slave mode: serial data input/output miim: data input/out note: an external pull - up is needed on this pin when it is in use. 44 nc nc unused pin, only this nc pin can be pulled down by a pull - down resistor for better emi. 45 p1anen ipu/o pu = enable auto - negotiation on port 1 pd = disable auto - negotiation on port 1 46 p1spd ipu/o pu = force port 1 to 100bt if p1anen = 0 pd = force port 1 to 10bt if p1anen = 0 47 p1dpx ipu/o pu = port 1 default to full duplex mode if p1anen = 1 and auto - negotiation fails. force port 1 in full - duplex mode if p1anen = 0. pd = port 1 default to half duplex mode if p1anen = 1 and auto - negotiation fails. force port 1 in half duplex mode if p1anen = 0. 48 gnd gnd digital ground downloaded from: http:/// micrel, inc. ksz8873mll/fll/rll september 20, 2013 16 revision 1.6 pin description and i/o assignment (continued) pin number pin name type (1) description 49 vddc p 1.8 v digital core power input from vddco ( p in 56). 50 p1ffc ipu/o pu = always enable (force) port 1 flow control feature pd = port 1 flow control feature enable is determined by auto negotiation result. 51 p3spd ipd/o pu = force port 3 to 10 bt pd = force port 3 to 10 0 bt (default) 52 nc nc unused pin. no external connection. 53 nc nc unused pin. no external connection. 54 vddio p 3.3v, 2.5v or 1.8v digital vdd input power supply for io with well decoupling capacitors. 55 gnd gnd digital ground 56 vddco p 1.8v core power voltage output (internal 1.8v ldo regulator output), this 1.8v output pin provides power to both vdda _ 1.8 and vdd c input pins. note: internally 1.8v ldo regulator input comes from vddio. do not connect an external power supply to vddco pin. the ferrite bead is requested between analog and digital 1.8v core power. 57 nc nc unused pin. no external connection. 58 p1led1 ip u /o port 1 led indicators : default: speed (refer to r egister 195 bit[5:4]) strap option : port 3 flow control selection(p3ffc) pu = always enable (force) port 3 flow control feature (default) pd = disable 59 p1led0 ip d /o port 1 led indicators : default: link/act. (refer to r egister 195 bit[5:4]) strap option : port 3 duplex mode selection(p3dp x) pu = port 3 to half duplex mode pd = port 3 to full duplex mode (default) note: p1led0 has weaker internal pull - down, recommend an external pull - down by a 0.5k resistor. downloaded from: http:/// micrel, inc. ksz8873mll/fll/rll september 20, 2013 17 revision 1.6 pin description and i/o assignment (continued) pin number pin name type (1) description 60 p2 led1 ip u /o port 2 led indicators : default: speed (refer to r egister 195 bit[5:4]) strap option : serial bus configuration port 2 led indicators : default: link/act. (refer to r egister 195 bit[5:4]) strap option : serial bus configuration serial bus configuration pins to select mode of access to ksz8873mll/fll/rll internal registers. [ p2led1, p2led0] = [0, 0] i 2 c master (eeprom) mode (if eeprom is not detected, the ksz8873mll/fll/rll will be configured with the default values of its regis ters and the values of its strap - in pins.) interface signals type description spiq o not used (tri - stated) scl _mdc o i 2 c clock sda _mdio i/o i 2 c data i/o spisn i not used [ p2led1, p2led0] = [0, 1] i 2 c slave mode the external i 2 c master will drive the scl _mdc clock. the ksz88 73mll/fll/rll device addresses are: 1011_1111 micrel, inc. ksz8873mll/fll/rll september 20, 2013 18 revision 1.6 pin description and i/o assignment (continued) pin number pin name type (1) description 63 fxsd1 i mll/rll: connect to analog ground by pull - down resistor. fll: fiber signal detect 64 vdd a_1.8 p 1.8 analog vdd input power supply from vddco ( p in 56 ) through external ferrite bead and capacitor s. notes: 1. speed : low (100base - tx), high (10base - t) full duplex : low (full duplex), high (half duplex) act : toggle (transmit / receive activity) link : low (link), high (no link) 2. p = power supply. gnd = ground. i = input. ipu/o = input with internal pull - up during reset, output pin otherwise. ipu = input w/ internal pull - up. ipd = input w/ internal pull - down. opu = output w/ internal pull - up. opd = output w/ internal pull - down. downloaded from: http:/// micrel, inc. ksz8873mll/fll/rll september 20, 2013 19 revision 1.6 functional description the ksz8873mll/fll/rll contains two 10/100 physical layer transceivers and three mac units wit h an integrated layer 2 managed switch. the ksz8873mll/fll/rll has the flexibility to reside in either a managed or unmanaged design. in a managed design, the host processor has complete control of the ksz8873mll/fll/rll via the smi inter face, miim interface, spi bus, or i 2 c bus. an unmanaged design is achieved through i/o strapping and/or eeprom programming at system reset time. on the media side, the ksz8873mll/fll/rll supports ieee 802.3 10base - t and 100base - tx on both phy ports . ph ysical signal transmission and reception are enhanced through the use of patented analog circui tries that make the design more efficient and allow for lower power consumption and smaller chip die size. functional overview: physical layer transceiver the 100base - tx transmit function performs parallel - to - serial conversion, 4b/5b coding, scrambling, nrz - to - nrzi c onversion, and mlt3 encoding and transmission. the circuitry starts with a parallel - to - serial conversion, which converts the mii data from the mac into a 125mhz serial bit stream. the data and control stream is then converted into 4b/5b coding, follow ed by a scrambler. the serialized data is further converted from nrz - to - nrzi format, and then transmitted in mlt3 current output. the output current i s set by an external1% 11.8 k ? resistor for the 1:1 transformer ratio. the output signal has a typical rise/fall time of 4ns and complies with the ans i tp - pmd standard regarding amplitude balance, overshoot, and timing jitter. the wave - shaped 10base - t output is also incorporated into the 100base - tx transmitter . 100base - tx transmit the 100base - tx receiver function performs adaptive equalization, dc restoration, mlt3 - to - nrzi conversion, data and clock recovery, nrzi - to - nrz conversion, de - scrambling, 4b/5b decoding, and serial - to - parallel conversion. the receiving side starts with the equalization filter to compensate for inter - symbol interference (isi) over the twisted pair cable. since the amplitude loss and phase distortion is a function of the cable length, the e qualizer must adjust its characteristics to optimize performance. in this design, the variable equalizer makes an ini tial estimation based on comparisons of incoming signal strength against some known cable characteristics, and th en tunes itself for optimization. this is an ongoing process and self - adjusts against environmental changes such as temperature variations. next, the equalized signal goes through a dc restoration and data conversion block. the dc r estoration circuit is used to compensate for the effect of baseline wander and to improve the dynamic range. t he differential data conversion circuit converts the mlt3 format back to nrzi. the slicing threshold is also adaptive. the clock recovery circuit extracts the 125mhz clock from the edges of the nrzi signal. this recovered clock is then used to convert the nrzi signal into the nrz format. this signal is sent through the de - scrambler followed by the 4b/5b decoder. finally, the nrz serial data is converted to the mii format and provided as the input data t o the mac. pll clock synthesizer the ksz8873mll/fll/rll generates 125 mhz, 62.5 mhz, and 31.25 mhz clocks for system timing. internal clocks are generated from an external 25mhz or 50mhz crystal or oscillator. ksz8873rll can generate a 50mhz reference clock for the rmii interface . scrambler/de - scrambler (100base - tx only) the purpose of the scrambler is to spread the power spectrum of the signal to reduce electromagneti c interference (emi) and baseline wander. transmitted data is scrambled through the use of an 11 - bit wide linear feedback shift register (lfsr). the scrambler generates a 2047 - bit non - repetitive sequence, and the receiver then de - scrambles the incoming data stream using the same sequence as at the transmitter . downloaded from: http:/// micrel, inc. ksz8873mll/fll/rll september 20, 2013 20 revision 1.6 100base - fx operation 100base - fx operation is similar to 100base - tx operation with the differences being that the scrambler/de - scrambler and mlt3 encoder/decoder are bypassed on transmission and reception. in addition, auto - negotiation is bypassed and auto mdi/mdi - x is disabled. 100base - fx signal detection in 100base - fx operation, fxsd (fiber signal detec t), input p in s 15 and 63, is usually connected to the fiber transceiver sd (signal detect) output pin. the fiber signal threshold can be selected by r egister 192 bit 7 and 6 respectively for port 2 and port 1, when fxsd is less than the threshold, no fiber signal is detected and a far - end fault (fef) is generated. when fxsd is over the threshold, the fiber signal is detected. alternatively, the designer may choose not to implement the fef feature. in this case, the fxsd input pin is tied high to force 100ba se - fx mode. 100base - fx signal detection is summarized in table 1 : table 1 . fx signal threshold register 192 bit 7 (port 2), bit 6 (port 1) fiber signal threshold at fxsd 1 2.0v 0 1.2v to ensure proper operation, a resistive voltage divider is recommended to adj ust the fiber transceiver sd output voltage swing to match the fxsd pins input voltage threshold. 100base - fx far - end fault a far - end fault (fef) occurs when the signal detection is logically false on the receive side of the fiber transceiver. the ksz88 73fll detects a fef when its fxsd input is fiber signal threshold. when a fef is detected, the ksz88 73fll signals its fiber link partner that a fef has occurred by sending 84 1s followed by a zero i n the idle period betwe en frames. by default, fef is enabled. fef can be disabled through register setting. 10base - t transmit the 10base - t driver is incorporated with the 100base - tx driver to allow for transmission using the same magnetics. they are internally wave - shaped and pr e- emphasized into outputs with a typical 2.3v amplitude. the harmonic contents are at least 27db below the fundamental frequency when driven by an all - ones manchester - encoded signal. 10base - t receive on the receive side, input buffers and level detecting squelch circuits are employed. a differential input receiver circuit and a phase - locked loop (pll) perform the decoding function. the manchester - encoded data stream is separated into clock signal and nrz data. a squelch circuit rejects signals with levels less than 400mv or with short pulse widths to prevent noise at the rxp - or - rxm input from falsely triggering the decoder. when the input exceeds the squelch limit, the pll locks onto the incoming signal and the ksz8873mll/fll/rll decodes a data frame. the receiver clock is maintained active during idle periods in between data reception. mdi/mdi - x auto crossover to eliminate the need for crossover cables between similar devices, the ksz8873mll/fll/rll support s hp auto mdi/mdi - x and ieee 802.3u standard mdi/mdi - x auto crossover. hp auto mdi/mdi - x is the default. the auto - sense function detects remote transmit and receive pairs and correctly assigns transmit and recei ve pairs for the ksz8873mll/fll/rll device. this feature is extremely useful when end users are unawar e of cable types, and also, saves on an additional uplink configuration connection. the auto - crossover feature can be disabled through the port control registers, or miim phy registers. downloaded from: http:/// micrel, inc. ksz8873mll/fll/rll september 20, 2013 21 revision 1.6 the ieee 802.3u standard mdi and mdi - x definitions are illustra ted in table 2 : table 2 . mdi/mdi - x pin definitions mdi mdi -x rj - 45 pins signals rj - 45 pins signals 1 td+ 1 rd+ 2 td - 2 rd - 3 rd+ 3 td+ 6 rd - 6 td - straight cable a straight cable connects an mdi device to an mdi - x device, or an mdi - x device to an mdi device. figure 1 depicts a typical straight cable connection between a nic card (mdi) and a switch, or hub (mdi - x). receive pair transmit pair receive pair 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 transmit pair modular connector (rj-45) nic straight cable 10/100 ethernet media dependent interface 10/100 ethernet media dependent interface modular connector (rj-45) hub (repeater or switch) figure 1. typical straight cable connection downloaded from: http:/// micrel, inc. ksz8873mll/fll/rll september 20, 2013 22 revision 1.6 crossover cable a crossover cable connects an mdi device to another mdi device, or an mdi - x device to another mdi - x device. figure 2 shows a typical crossover cable connection between two switches or hubs (two mdi - x dev ices) : receive pair receive pair transmit pair 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 transmit pair 10/100 ethernet media dependent interface 10/100 ethernet media dependent interface modular connector (rj-45) hub (repeater or switch) modular connector (rj-45) hub (repeater or switch) crossover cable figure 2 . typical crossover cable connection downloaded from: http:/// micrel, inc. ksz8873mll/fll/rll september 20, 2013 23 revision 1.6 auto - negotiation the ksz8873mll/fll/rll conforms to the auto - negotiation protocol, defined in clause 28 of the ieee 802.3u specification. auto - negotiation allows unshielded twisted pair (utp) link partners to select the best common mode of operation. in auto - negotiation, link partners advertise their capabilities across the link to each other. if auto - negotiation is not supported or the ksz8873mll/fll/rll link partner is forced to bypass auto - negotiation, the ksz8873mll/fll/rll sets its operating mode by observing the signal at its receiver. this is known as parallel detection, and allow s the ksz8873mll/fll/rll to establish link by listening for a fixed signal protocol in the absence of auto - negotiation advertisement protocol. the link up process is shown in figure 3: start auto negotiation force link setting listen for 10base -t link pulses listen for 100base - tx idles attempt auto negotiation link mode set bypass auto negotiation and set link mode link mode set ? parallel operation join flow n o yes yes no figure 3 . auto - negotiation and parallel operation downloaded from: http:/// micrel, inc. ksz8873mll/fll/rll september 20, 2013 24 revision 1.6 linkmd ? cable diagnosti cs ksz8873mll/fll/rll supports the linkmd ? . the linkmd ? feature utilizes time domain reflectometry (tdr) to analyze the cabling plant for common cabling problems such as open circuits, short circuits and impedance mismat ches. linkmd ? works by sending a pulse of known amplitude and duration down the mdi and mdi - x pairs and then analyzes the shape of the reflected signal. timing the pulse duration gives an indication of the distance to t he cabling fault. intern al circuitry displays the tdr information in a user - readable digital format. note : cable diagnostics are only valid for copper connections and do not support fiber optic operation. access linkmd ? is initiated by accessing the phy special control/status r egister s {26, 42} and the linkmd result registers { 27 , 43} for ports 1 and 2 respectively; and in conjunction with the port registers control 13 for ports 1 and 2 respectively to disable auto mdi/mdix . alternatively, the miim phy registers 0 and 29 can be used for linkmd ? access. usag e the following is a sample procedure for using linkmd ? with registers { 42,43,45 } on port 2: 1. disable auto mdi/mdi -x by writing a 1 to r egister 45 , bit [2] to enable manual control over the differential pair used to transmit the linkmd ? pulse. 2. start cable diagnostic test by writing a 1 to r egister 42 , bit [4]. this enable bit is self - clearing. 3. wait (poll) for r egister 42 , bit [4] to return a 0, indicating cable diagnostic test is completed. 4. read cable diagno stic test results in r egister 42 , bits [6:5] . the results are as follows: 00 = normal condition (valid test) 01 = open condition detected in cable (valid test) 10 = short condition detected in cable (valid test) 11 = cable diagnostic test failed (invalid test) the 11 case, invalid test, occurs when the ksz8873mll/fll/rll is unable to shut down the link par tner. in this instance, the test is not run, since it would be impossible for the ksz8873mll/fll/rll to d etermine if the detected signal is a reflection of the signal generated or a signal from another source. 5. get distance to fault by concatenating r egister 42 , bit [0] and r egister 43 , bits [7:0]; and multiplying the result by a constant of 0.4. the distance to the cable fault can be determined by the following formula: d (distance to cable fa ult) = 0.4 x {( r egister 26, bit [0]),(r egister 27, bits [7:0])} d (distance to cable fault) is expressed in meters. co ncatenated value of r egister s 42 and 43 is converted to decimal before multiplying by 0.4. the constant (0.4) may be calibrated for different cabling conditions, including cables wit h a velocity of propagation that varies significantly from the norm. downloaded from: http:/// micrel, inc. ksz8873mll/fll/rll september 20, 2013 25 revision 1.6 functional overview: power management the ksz8873mll/fll/rll supports enhanced power management feature in low power state with energy d etection to ensure low - power dissipation during device idle periods. there are five operation modes under the power management function which is controlled by two bits in register 195 (0x c3 ) and one bit in register 29 (0x1d),45(0x2d) as shown below: regist er 195 bit[1:0] = 00 normal operation mode register 195 bit[1:0] = 01 energy detect mode register 195 bit[1:0] = 10 soft power - down mode register 195 bit[1:0] = 11 power - saving mode register 29,45 bit 3 =1 port - based power - down mode table 3 indicates all internal function blocks status under four different power management operation modes. table 3 . internal function block status ksz8873mll/fll/rll function blocks power management operation modes normal mode power saving mode energy detect mode soft power down mode internal pll clock enabled enabled disabled disabled tx/rx phy enabled rx unused block disabled energy detect at rx disabled mac enabled enabled disabled disabled host interface enabled enabled disabled disabled normal operation mode this is the default setting bit[1:0]=00 in r egister 195 after the chip power - up or hardware reset . when ksz8873mll/fll/rll is in this normal operation mode, all pll clocks are runn ing, phy and mac are on and the h ost interface is ready for cpu read or write. during the normal operation mode, the host cpu can set the bit[1:0] in r egister 195 to transit the current normal operation mode to any one of the other three power management operation modes. energy - detect mo de the energy - detect mode provides a mechanism to save more power than in the normal operation mode when the ksz8873mll/fll/rll is not connected to an active link partner. in this mode, the device wil l save up to 50% of the power. if the cable is not plugg ed , the ksz8873mll/fll/rll can automatically enter to a low power state, a.k.a., the energy - detect mode. in this mode, ksz8873mll/fll/rll will keep transmitting 120ns width pulses at 1 pulse/s rate. once activity resumes due to plugging a cable or attempting by the far end to e stablish link, the ksz8873mll/fll/rll can automatically power up to normal power state in energy detect mode. energy detect mode consists of two states, normal power state and low power state. while in lo w power state, the ksz8873mll/ fll/rll reduces power consumption by disabling all circuitry except the energy det ect circuitry of the receiver. the energy detect mode is entered by setting bit[1:0]=01 in r egister 195 . when the ksz8873mll/fll/rll is in this mode, it will monitor the cable energy. if there is no energy on the cable for a tim e longer than pre - configured value at bit[7:0] go - sleep time in r egister 196 , ksz8873mll/fll/rll will go into a low power state. when ksz8873mll/fll/rll is in low power state, it will keep monitoring t he cable energy. once the energy is detected from the cable , ksz8873mll/fll/rll will enter normal power state . when ksz8873mll/fll/rll is at normal power state, it is able to transmit or receive packet from the cable. it will save about 87% of the power when mii interface is in phy mode, p in smtxer3/mii_link_3 is connected to high, r egister 195 bit [1:0] =01, bit 2 =1(disable pll), not cables are connected. downloaded from: http:/// micrel, inc. ksz8873mll/fll/rll september 20, 2013 26 revision 1.6 soft power - down mode the soft power - down mode is entered by setting bit[1:0]=10 in r egister 195 . when ksz8873mll/fll/rll is in this mode, all pll clocks are disabled, the phy and the mac are off, all internal registers value will not change . when the host set bit[1:0]= 0 0 in r egister 195 , this device will be back from current soft power down mode to normal operation mode power - saving mode the power saving mode is entered when auto - negotiation mode is enabled, cable is disconnected, and by setting bit[1:0]=11 in r egister 195 . when ksz8873mll/fll/rll is in this mode, all pll clocks are enabled, mac is on, all internal registers value will not change, and host interface is ready for cpu read or write. in this mode, it mainly controls the phy transceiver on or off based on line status to achieve power saving. the phy remains transmitting and only turns of f the unused receiver block. once activity resumes due to plugging a cable or attempting by the far end to establish link, the ksz8873mll/fll/rll can automatically enabled the phy power up to normal power state f rom power saving mode. during this power saving mode, the host cpu can set bit[1:0] =0 in r egister 195 to transit the current power saving mode to any one of the other three power management operation modes. port -b ased power - down mode in addition, t he ksz8873mll/fll/rll features a per - port power - dow n mode. to save power, a phy port that is not in use can be powered down via port control r egister 29 or 45 bit 3, or miim phy register. it will saves about 15ma per port. hardware power down ksz8873 supports a hardware power - down mode. when the p in pwrdn is activated low, the entire chip is powered down. downloaded from: http:/// micrel, inc. ksz8873mll/fll/rll september 20, 2013 27 revision 1.6 functional overview: mac and switch address lookup the internal lookup table stores mac addresses and their associated information. it contains a 1k unicast address table plus switching information. the ksz8873mll/fll/rll is guaranteed to learn 1k addresses and distinguishes its elf from hash - based lookup tables, which depending on the operating environment and probabilities, may not guarantee the absolute number of addres ses it can learn. learning the internal lookup engine updates its table with a new entry if the following conditions ar e met: 1. the received packet's source address (sa) does not exist in the lookup table. 2. the received packet is good; the packet has no receiving errors, and is of legal len gth. the lookup engine inserts the qualified sa into the table, along with the port number and time st amp. if the table is full, t he last entry of the table is deleted to make room for the new entry. migration the internal lookup engine also monitors whether a station has moved. if a station has moved, it w ill update the table accordingly. migration happens when the following conditions are met: 1. the received packet's sa is in the table but the associated source port information is differ ent. 2. the received packet is good; the packet has no receiving errors, and is of legal length. the lookup engine will update the existing record in the table with the new source port informati on. aging the lookup engine updates the time stamp information of a record whenever the corresponding sa appears. the time stamp is used in the aging process. if a record is not updated for a period of tim e, the lookup engine removes the record from the table. the lookup engine constantly performs the aging process and will continuousl y remove aging records. the aging period is about 200 seconds. this feature can be enabled or disabled through r egister 3 (0x03) bit [2]. forwarding the ksz8873mll/fll/rll forwards packets using the algorithm that is depicted in the following flow charts. figure 4 shows stage one of the forwarding algorithm where the search engine looks up the vla n id, static table, and dynamic table for the destination address, and comes up with port to forward 1 (ptf1). ptf1 is then further modif ied by spanning tree, igmp snooping, port mirroring, and port vlan processes to c ome up with port to forward 2 (ptf2), as shown in figure 5. the packet is sent to ptf2. downloaded from: http:/// micrel, inc. ksz8873mll/fll/rll september 20, 2013 28 revision 1.6 start vlan id valid? ptf1= null search static table search complete. get ptf1 f rom static mac table dy namic table search search complete. get ptf1 f rom vlan table search complete. get ptf1 f rom dy namic mac table ptf 1 - search vlan table - ingress vlan f iltering - discard npvid check y es no found not found found not found this search is based on da or da+fid this search is based on da+fid figure 4 . destination address lookup flow chart ? stage 1 downloaded from: http:/// micrel, inc. ksz8873mll/fll/rll september 20, 2013 29 revision 1.6 spanning tree process ptf1 igmp process port mi rror process port vlan membership check ptf2 - check receiving port's receive enable bit - check destination port's transmit enable bit - check whether packets are special (bpdu or specified) - rx mi rror - t x mi rror - rx or t x mi rror - rx and tx mirror - applied to mac #1 and mac #2 - mac #3 is reserved for microprocessor - igmp will be forwarded to port 3 figure 5 . destination address resolution flow chart ? stage 2 the ksz8873mll/fll/rll will not forward the following packets: 1. error pa ckets these include framing errors, frame check sequence (fcs) errors, alignment errors, and illegal si ze packet errors. 2. ieee802.3x pause frames ksz8873mll/fll/rll intercepts these packets and performs full duplex flow control accord ingly. 3. "local" packe ts based on destination address (da) lookup. if the destination port from the lookup table matches the port from w hich the packet originated, the packet is defined as "local." downloaded from: http:/// micrel, inc. ksz8873mll/fll/rll september 20, 2013 30 revision 1.6 switching engine the ksz8873mll/fll/rll features a high - performance switching engine to move data to and from the macs packet buffers. it operates in store and forward mode, while the efficient switching mechanism reduces ov erall latency. the switching engine has a 32kb internal frame buffer. this buffer pool is shared between all three ports. there are a total of 256 buffers available. each buffer is sized at 128 bytes. mac operation the ksz8873mll/fll/rll strictly abides by ieee 802.3 standards to maximize compatibi lity. inter packet gap (ipg) if a frame is successfully transmitted, the 96 bits time ipg is measured between the two consec utive mtxen. if the current packet is experiencing collision, the 96 bits time ipg is measured from mcrs and the next mtxen. back - off algorithm the ksz8873mll/fll/rll implements the ieee 802.3 standard for the binary exponential back - off algorithm, and optional "aggressive mode" back - off. after 16 collisions, the packet is optionally dropped depending on the switch configuration for r egister 4 (0x04) bit [3]. late collision if a transmit packet experiences collisions after 512 bit times of the transmission, the packet is dropped. illegal frames the ksz8873mll/fll/rll discards frames less than 64 bytes, and can be programmed to accept frames up to1518 bytes, 1536 bytes or 1916 bytes. these maximum frame size settings are program med in r egister 4 (0x04). since the ksz8873mll/fll/rll supports vlan tags, the maximum sizing is adjusted when these tags are present. full duplex flow control the ksz8873mll/fll/rll supports standard ieee 802.3x flow control frames on both transmit and rec eive sides. on the receive side, if the ksz8873mll/fll/rll receives a pause control frame, the ksz8873mll/fll/rll will not transmit the next normal frame until the timer, specified in the pause control frame, expires. if another pause frame is received before the current timer expires, the timer will be updated with the new value in the second pause frame. during this period (while it is flow controlled), only flow control packets from t he ksz8873mll/fll/rll are transmitted. on the transmit side, the ksz8873mll/fll/rll has intelligent and efficient ways to determine whe n to invoke flow control. the flow control is based on availability of the system resources, including availabl e buffers, available transmit queues and available receive queues. the ksz8873mll/fll/rll will flow control a port that has just received a packet if the d estination port resource is busy. the ksz8873mll/fll/rll issues a flow control frame (xoff), containing the maximum pause tim e defined by the ieee 802.3x standard. once the resource is freed up, the ksz8873mll/fll/rll sends out the other flow control fra m e (xon) with zero pause time to turn off the flow control (turn on transmission to the port). a hyster esis feature is provided to prevent the flow control mechanism from being constantly activated and deactivated. the ksz8873mll/fll/rll flow controls all ports if the receive queue becomes full. half - duplex backpressure a half - duplex backpressure option (not in ieee 802.3 standards) is also provided. the activation and deactivat ion conditions are the same as full duplex flow control. if backpressure is required, the ks z8873mll/fll/rll sends preambles to defer the other stations' transmission (carrier sense deference). downloaded from: http:/// micrel, inc. ksz8873mll/fll/rll september 20, 2013 31 revision 1.6 to avoid jabber and excessive deference (as defined in the 802.3 standard), after a certain time, the ksz8873mll/fll/rll discontinues the carrier sense and then raises it again quickly . this short silent time (no carrier sense) prevents other stations from sending out packets thus keeping other stations i n a carrier sense deferred state. if the port has packets to send during a backpressure situation, the carrier sense type backpressure is interrupted and t hose packets are transmitted instead. if there are no additional packets to send, carrier sense type backpress ure is reactivated again until switch resources free up. if a collision occurs, the binary ex ponential back - off algorithm is skipped and carrier sense is generated immediately, thus reducing the chance of further collisions and car rier sense is maintained to prevent packet reception. to ensure no packet loss in 10 base - t or 100 base - tx half duplex modes, the user must enable the following: 1. aggressive back - off ( r egister 3 (0x03), bit [0]) 2. no excessive collision drop ( r egister 4 (0x04), bit [3]) note : these bits are not set as defaults, as this is not the ieee standard. broadcast storm p rotection the ksz8873mll/fll/rll has an intelligent option to protect the switch system from receiving too many broadcast packets. as the broadcast packets are forwarded to all ports except the source port, an excessi ve number of switch resources (bandwidth and available space in transmit queues) may be utilized. the ksz8873mll/fll/rl l has the option to include multicast packets for storm control. the broadcast storm rate par ameters are programmed globally, and can be enabled or disabled on a per port basis. the rate is based on a 67ms interval for 100bt and a 500ms interval for 10bt. at the beginning of each interval, the counter is cleared to zero, and the r ate limit mechanism starts to count the number of bytes during the interval. the rate definition is described in r egister 6 (0x06) and 7 (0x07). the default setting is 0x63 (99 decimal). this is equal to a rate of 1%, calculated as follows: 148,800 frames/sec * 67ms/interval * 1% = 99 frames/interval (approx.) = 0x63 note : 148,800 frames/sec is based on 64 - byte block of packets in 100base - tx with 12 bytes of ipg and 8 bytes of preamble between two packets. port individual mac address and source port filtering the ksz8873mll/fll/rll provide individual mac address for port 1 and port 2 respectively. t hey can be set at r egister 142 - 147 and 148 - 153. with this feature, the cpu connected to the port 3 can receive the packets from two internet subnets which has their own mac address. the packet will be filtered if its source address matches the mac address of port 1 or port 2 when the r egister 21 and 37 bit 6 is set to 1 respectively. for example, the packet will be dropped after it completes the loop of a ring network. mii interface operation the media independent i nterface (mii) is specified in clause 22 of the ieee 802.3u standard. it provides a common interface between physical layer and mac layer devices. the mii pro vided by the ksz8873mll/fll is connected to the devices third mac. the interface contains two distinct groups of signals: one for transmiss ion and the other for reception. table 4 describes the signals used by the mii bus. downloaded from: http:/// micrel, inc. ksz8873mll/fll/rll september 20, 2013 32 revision 1.6 table 4 . mii signals phy - mode connections mac - mode connections external mac controller signals ksz8873mll/fl phy signals pin descriptions external phy signals ksz8873mll/fll mac signals mtxen smtxen 3 transmit enable mtxen smrxdv 3 mtxer smtxer 3 transmit error mtxer (not used) mtxd3 smtxd 33 transmit data bit 3 mtxd3 smrxd 33 mtxd2 smtxd 32 transmit data bit 2 mtxd2 smrxd 32 mtxd1 smtxd 31 transmit data bit 1 mtxd1 smrxd 31 mtxd0 smtxd 30 transmit data bit 0 mtxd0 smrxd 30 mtxc smtxc 3 transmit clock mtxc smrxc 3 mcol scol 3 collision detection mcol scol 3 mcrs scrs 3 carrier sense mcrs scrs 3 mrxdv smrxdv 3 receive data valid mrxdv smtxen 3 mrxer (not used) receive error mrxer smtxer 3 mrxd3 smrxd 33 receive data bit 3 mrxd3 smtxd 33 mrxd2 smrxd 32 receive data bit 2 mrxd2 smtxd 32 mrxd1 smrxd 31 receive data bit 1 mrxd1 smtxd 31 mrxd0 smrxd 30 receive data bit 0 mrxd0 smtxd 30 mrxc smrxc 3 receive clock mrxc smtxc 3 the mii operates in either phy mode or mac mode. the data interface is a nibble wide and runs at ? the network bit r ate (not encoded). additional signals on the transmit side indicate when data is valid or when an error occur s during transmission. similarly, the receive side has signals that convey wh en the data is valid and without physical layer errors. for half duplex operation, the scol signal indicates if a collision has occurred during transmis sion. the ksz8873mll/fll does not provide the mrxer signal for phy mode operation and the mtxer signal for mac mode operation. normally, mrxer indicates a receive error coming from the physical layer device and mtxer indicates a transmit error from the mac device. since the switch filters error fram es, these mii error signals are not used by the ksz88 73mll/fll . so, for phy mode operation, if the device interfacing with the ksz 8873mll/fll has an mrxer input pin, it needs to be tied low. and, for mac mode operation, if the device interfacing w ith the ksz8873mll/fll has an mtxer input pin, it also needs to be tied low. the ksz8873m ll/fll provides a bypass feature in the mii phy mode. pin smtxer3/mii_link is used for mii link status. if the host is power down, p in mii_link will go to high . in this case, no new ingress frames from port 1 or port 2 will be sent out through port 3, and the frames for port 3 already in packet memory will be flushed out. rmii interface operation the reduced media independent interface (rmii) specifies a low pin count media independent interfac e (mii). rmii provides a common interface between physical layer and mac layer devices, and has the follow ing key characteristics: 1. p orts 10mbps and 100mbps data rates. 2. uses a single 50 mhz clock reference (provided inte rnally or externally). 3. provides independent 2 - bit wide (di - bit) transmit and receive data paths. 4. contains two distinct groups of signals: one for transmission and the other for reception when en_refclko_3 is high, ksz8873rll will output a 50mhz in refclko_3. register 198 bit[3] is used to select internal or external reference clock. internal reference clock means that the clo ck for the rmii of ksz8873rll will be downloaded from: http:/// micrel, inc. ksz8873mll/fll/rll september 20, 2013 33 revision 1.6 provided by the ksz8873rll internally and the refclki_3 pin is unconnected. for the external reference cl ock, the clock will provide to ksz8873rll via refclki_3. note : if the reference clock is not provided by the ksz8873rll, this 50mhz refer ence clock has to be used in x1 pin instead of the 25mhz crystal since the clock skew of these two clock so urces will impact on the rmii timing. the spiq clock selection strapping option pin is connected to low to select the 50mhz input. table 5 . rmii clock setting reg198[3] en_refclko_3 clock source note 0 0 external 50mhz osc input to refclki_3 en_refclko_3 = 0 to disable refclko_3 for better emi 0 1 refclko_3 output is feedback to refclki_3 en_refclko_3 = 1 to enable refclko_3 1 1 internal clock source refclki_3 is unconnected en_refclko_3 = 1 to enable refclko_3 1 0 not suggest ed the rmii provided by the ksz8873rll is connected to the devices third mac . it complies with the rmii specification. table 6 describes the signals used by the rmii bus. refer to rmii specification for full deta il on the signal description. table 6 . rmii signal description rmii signal name direction (with respect to the phy) direction (with respect to the mac) rmii signal description ksz8873rll rmii signal (direction) ref_clk input input or output synchronous 50 mhz clock reference for receive, transmit and control interface refclki_3 (input) crs_dv output input carrier sense/receive data valid smrxdv3 (output) rxd1 output input receive data bit 1 smrxd31 (output) rxd0 output input receive data bit 0 smrxd30 (output) tx_en input output transmit enable smtxen3 (input) txd1 input output transmit data bit 1 smtxd31 (input) txd0 input output transmit data bit 0 smtxd30 (input) rx_er output input (not required) receive error (not used) ? ? ? ? smtxer3* (input) * connects to rx_er signal of rmii phy device downloaded from: http:/// micrel, inc. ksz8873mll/fll/rll september 20, 2013 34 revision 1.6 the ksz8873rll filters error frames, and thus does not implement the rx_er output signal. to det ect error frames from rmii phy devices, the smtxer 3 input signal of the ksz8873rll is connected to the rxer output signal of the rmii phy device. collision detection is implemented in accordance with the rmii specification. in rmii mode, tie mii signals, smtxd 3 [3:2] and smtxer 3 , to ground if they are not u sed. the ksz8873rll rmii can interface with rmii phy and rmii mac devices. th e latter allows two ksz8873rll devices to be connected back - to - back. table 7 shows the ksz8873rll rmii pin connections with an external rmii phy and an external rmii mac, such as another ksz8873rll device. table 7 . rmii signal connections ksz8873rll phy - mac connections ksz8873rll mac - mac connections external phy signals ksz8873rll mac signals pin descriptions ksz8873rll mac signals external mac signals ref_clk refclk i_3 reference clock refclk i_3 ref_clk tx_en smrxdv 3 carrier sense/ receive data valid smrxdv 3 crs_dv t xd1 smrxd 31 receive data bit 1 smrxd 31 rxd1 t xd0 smrxd 30 receive data bit 0 smrxd 30 rxd0 crs_dv smtxen 3 transmit enable smtxen 3 tx_en r xd1 smtxd 31 transmit data bit 1 smtxd 31 txd1 r xd0 smtxd 30 transmit data bit 0 smtxd 30 txd0 rx_er smtxer 3 receive error (not used) (not used) mii management (miim) interface the ksz8873mll/fll/rll supports the ieee 802.3 mii management interface, also known as the management d ata input/output (mdio) interface. this interface allows upper - layer devices to monitor and control the states of the ksz8873mll/fll/rll. an external device with mdc/mdio capability is used to read the phy s tatus or configure the phy settings. further detail on the miim interface is found in clause 22.2.4.5 of the ieee 802.3u specification and refer to 802.3 section 22.3.4 for the timing . the miim interface consists of the following: ? a physical connection that incorporates the data line ( sda_ mdio) and the clock line ( scl_ mdc). ? a specific protocol that operates across the aforementioned physical connect ion that allows an external controller to commun icate with the ksz8873mll/fll/rll device. ? access to a set of eight 16 - bit registers, consisting of six standard miim registers [0:5] and two custom miim regist ers [29, 31]. the miim interface can operate up to a maximum clock speed of 5mhz. downloaded from: http:/// micrel, inc. ksz8873mll/fll/rll september 20, 2013 35 revision 1.6 table 8 depic ts the mii management interface frame format. table 8 . mii management interface frame format preamble start of frame read/write op code phy address bits [4:0] reg address bits [4:0] ta data bits [15:0] idle read 32 1s 01 10 aaaaa rrrrr z0 dddddddd_dddddddd z write 32 1s 01 01 aaaaa rrrrr 10 dddddddd_dddddddd z serial management interface (smi) the smi is the ksz8873mll/fll/rll non - standard miim interface that provides access to all ksz8873mll/fll/rll configuration registers. this interface allows an external device to completely monitor and cont rol the states of the ksz8873mll/fll/rll. the smi interface consists of the following: ? a physical connection that incorporates the data line ( sda_ mdio) and the clock line ( scl_ mdc). ? a s pecific protocol that operates across the aforementioned physical connection that allows an external controller to communicate with the ksz8873mll/fll/rll device. ? access to all ksz8873mll/fll/rll configuration registers. register access includes the g lo bal , port and advanced control registers 0 - 198 (0x00 C 0x c6 ), and indirect access to the standard miim registers [0:5] and custom miim registers [29, 31]. table 9 depicts the smi frame format. table 9. serial management interface (smi) frame format preamble start of frame read/write op code phy address bits [4:0] reg address bits [4:0] ta data bits [15:0] idle read 32 1s 01 00 1xrrr rrrrr z0 0000_0000_dddd_dddd z write 32 1s 01 00 0xrrr rrrrr 10 xxxx_xxxx_dddd_dddd z smi register read access is selected when op code is set to 00 and bit 4 of the phy address is set to 1. smi register write access is selected when op code is set to 00 and bit 4 of the phy address is set to 0. phy address bit[3] is undefined for smi register access, and hence can be set to either 0 or 1 in read/write oper ations. to access the ksz8873mll/fll/rll r egister s 0 - 196 (0x00 C 0x c6 ), the following applies: ? phyad[2:0] and regad[4:0] are concatenated to form the 8- bit address; that is, {phyad[2:0], regad[4:0]} = bits [7:0] of the 8 - bit address. ? ta bits [1:0] are z0 means the processor mdio pin is changed to input hi - z from output mode and the followed 0 is the read response from device . ? ta bits [1:0] are set to 1 0 when write registers. ? registers are 8 data bits wide. ? for read operation, data bits [15:8] are read back as 0s. ? for write operation, data bits [15:8] are not defined, and hence can be set to either 0 or 1. smi register access is the same as the miim register access, except for the regi ster access requirements presented in this section. downloaded from: http:/// micrel, inc. ksz8873mll/fll/rll september 20, 2013 36 revision 1.6 advanced switch functions bypass mode the ksz8873mll/fll/rll also offer a by - pass mode which enables system - level power saving . when the cp u (connected to port 3) enters a power saving mode of power down or sleeping mode , the cpu can control the p in 27 smtxer3/mii_link_3 which can be tied high so that the ksz8873mll/fll/rll detect this change and a utomatically switches to the by - pass mode in which the switch function between port1 and port2 is sustained. in the by - pass mode, the packets with da to port 3 will be dropped and by pass the internal buffer memory, make the buffer memory more efficiency for the data transfer between port 1 and port 2. specially, the power saving get more in energy detect mode with the by - pass to be used. ieee 802.1q vlan support the ksz8873mll/fll/rll supports 16 active vlans out of the 4096 possible vlans specified in the ieee 802.1q specification. ksz8873mll/fll/rll provides a 16 - entries vlan table, which converts the 12 - bits vlan id (vid) to the 4- bits filter id (fid) for address lookup. if a non - tagged or null - vid - tagged packet is received, the ingress port default vid is used for lookup. in vlan mode, the lookup process starts with vlan table lookup t o determine whether the vid is valid. if the vid is not valid, the packet is dropped and its address is not learned. if the vid is valid, the fid is retrieved for further lookup. the fid + destination address (fid+da) are used to determine the destination port. the fid + source address (fid+sa) are used for address learning. table 10 . fid + da lookup in vlan mode da found in static mac table? use fid flag? fid match? da+fid found in dynamic mac table? action no dont care dont care no broadcast to the membership ports defined in the vlan table bits [18:16] no dont care dont care yes send to the destination port defined in the dynamic mac address table bits [53:52] yes 0 dont care dont care send to the destination port(s) defined in the static mac address table bits [50:48] yes 1 no no broadcast to the membership ports defined in the vlan tabl e bits [18:16] yes 1 no yes send to the destination port defined in the dynamic mac address ta ble bits [53:52] yes 1 yes dont care send to the destination port(s) defined in the static mac address table bits [50:48] table 11 . fid + sa lookup in vlan mode fid+sa found in dynamic mac table? action no learn and add fid+sa to the dynamic mac address table yes update time stamp advanced vlan features, such as ingress vlan filtering and discard non pv id packets are also supported by the ksz8873mll/fll/rll. these features can be set on a per port basis, and are defined in register 18, 34 and 50 for ports 1, 2 and 3, respectively. downloaded from: http:/// micrel, inc. ksz8873mll/fll/rll september 20, 2013 37 revision 1.6 qos priority support the ksz8873mll/fll/rll provides quality of service (qos) for applications such as voip and video c onferencing. offering four priority queues per port, the per - port transmit queue can be split into four priority queues: queue 3 is the highest priority queue and queue 0 is the lowest priority queue. bit [0] of r egister s 16, 32 and 48 is used to enable split transmit queues for ports 1, 2 and 3, respectively. if a port's transmit queue is not split, high priori ty and low priority packets have equal priority in the transmit queue. there is an additional option to either always deliver high priority pac kets first or use weighted fair queuing for the four priority queues. this global option is set and explained in bit [3] of r egister 5. port - based priority with port - based priority, each ingress port is individually classified as a high priority recei ving port. all packets received at the high priority receiving port are marked as high priority and are sent to the high - priority transmit queue if the corresponding transmit queue is spli t. bits [4:3] of r egister s 16, 32 and 48 are used to enable port - based priority for ports 1, 2 and 3, respectively. 802.1p - based priority for 802.1p - based priority, the ksz8873mll/fll/rll examines the ingress (incoming) packets to determine wheth er they ar e tagged. if tagged, the 3 - bit priority field in the vlan tag is retrieved and compared against the priority mapping value, as specified by the r egister s 12 and 13. the priority mapping value is programmable. figure 6 illustrates how the 802.1p priority field is embedded in the 802.1q vlan tag. preamble da tci 8 6 6 2 length llc data fcs 2 46-1500 4 1 tagged packet type (8100 for ethernet) 802.1p cfi vlan id bytes bits 16 3 12 802.1q vlan tag 2 sa vpid figure 6 . 802.1p priority field format 802.1p - based priority is enabled by bit [5] of r egister s 16, 32 and 48 for ports 1, 2 and 3, respectively. the ksz8873mll/fll/rll provides the option to insert or remove the priority tagg ed frame's header at each individual egress port. this header, consisting of the 2 bytes vlan protocol id ( vpid) and the 2 - byte tag control information field (tci), is also referred to as the ieee 802.1q vlan tag. tag insertion is enabled by bit [2] of the port registers control 0 and the r egister 194 to select which source port (ingress port) pvid can be inserted on the egress port for ports 1, 2 and 3, respectively. at the egress port, untagged packets are tagged with the ingress ports default tag. the default tags are programmed in regis ter sets {19,20}, {35,36} and {51,52} for ports 1, 2 and 3, respectively and the source port vid has to be inserted at selected egress ports by bit[5:0] of register 194 . the ksz8873mll/fll/rll will not add tags to already tagged packets. tag removal is enabled by bit [1] of r egister s 16, 32 and 48 for ports 1, 2 and 3, respectively. at the egress port, tagged packets will have their 802.1q vlan tags removed. the ksz8873mll/fll/rll will not modify unt agged packets. the crc is recalculated for both tag insertion and tag removal. downloaded from: http:/// micrel, inc. ksz8873mll/fll/rll september 20, 2013 38 revision 1.6 802.1p priority field re -m apping is a qos feature that allows the ksz8873mll/fll/rll to set the user priority ceiling at any ingress port. if the ingress packets priority field has a higher priority value than the default tags prior ity field of the ingress port, the packets priority field is replaced with the default tag s priority field. dif fserv - based priority diffserv - based priority uses the tos registers ( r egister s 96 to 111) in the advanced control registers section. the tos priority control registers implement a fully decoded, 64 - bit differentiated services code point (dscp) register to determine packet priority from the 6 - bit tos field in the ip header. when the most significant 6 bits of the tos field are fully decoded, the resultant of the 64 possibilities is compared with the corresponding bi ts in the dscp register to determine priori ty. spanning tree support to support spanning tree, port 3 is designated as the processor port. the other ports (port 1 and port 2) can be configured in one of the five spanning tree states via transmit enable, receive enable and learning disable register settings in r egister s 18 and 34 for ports 1 and 2, respectively. table 12 shows the port setting and software actions taken for each of the five spanning tree states. table 12 . spanning tree states disable state port setting software action the port should not forward or receive any packets. learning is disabled. transmit enable = 0, receive enable = 0, learning disable =1 the processor should not send any packets to the port. the switch may still send specific packets to the processor (packets that match some entries in the static mac table with overriding bit set) and the processor should discard those packets. address learning is disabled on the port in this state. blocking state port setting software action only packets to the processor are forwarded. learning is disabled. transmit enable = 0, receive enable = 0, learning disable =1 the processor should not send any packets to the port( s) in this state. the processor should program the static mac table with the entries that it needs to receive (for example, bpdu packets). the overriding bit should also be set so that the switch will forward those specific packets to the processor. ad dress learning is disabled on the port in this state. listening state port setting software action only packets to and from the processor are forwarded. learning is disabled. transmit enable = 0, receive enable = 0, learning disable =1 the processor should program the static mac table with the entries that it needs to receive (for example, bpdu packets). the overriding bit should be set so that the switch will forward those specific packets to the processor. the processor may send packets to the port(s) in this state. see tail tagging mode for details. address learning is disabled on the port in this state. learning state port setting software action only packets to and from the processor are forwarded. learning is enabled. transmit enable = 0 , receive enable = 0, learning disable = 0 the processor should program the static mac table with the entries that it needs to receive (for example, bpdu packets). the overriding bit should be set so that the switch will forward those specific packets to the processor. the processor may send packets to the port(s) in this state. see tail tagging mode for details. address learning is enabled on the port in this state. forwarding state port setting software action packets are forwarded and received normally. learning is enabled. transmit enable = 1, receive enable = 1, learning disable = 0 the processor programs the static mac table with the entries that it needs to receive (for example, bpdu packets). the overriding bit is set so that the switch forwards those specific packets to the processor. the processor can send packets to the port(s) in this state. see tail tagging mode for details. address learning is enabled on the port in this state. downloaded from: http:/// micrel, inc. ksz8873mll/fll/rll september 20, 2013 39 revision 1.6 rapid spanning tree support there are three operational states of the discarding, learning, and forwarding assigned to each port f or rstp: discarding ports do not participate in the active topology and do not learn mac addresses. discarding state: the state includs three states of the disable, blocking and listening of stp . port setting: "transmit enable = 0, receive enable = 0, learning disable = 1." software action: the processor should not send any packets to the port. the sw itch may still send specific packets to the processor (packets that match some entries in the static table with over riding bit set) and the processor should discard those packets. when disable the ports learning capability (learning disable=1), s et the r egister 2 bit 5 and bi t 4 will flush rapidly the port related entries in the dynamic mac table and static mac table. note : processor is connected to port 3 via mii interface. address learning is disabled on the port in this state. ports in learning states learn mac addresses, but do not forward user traffic. learnin g state: only packets to and from the processor are forwarded. learning is enabled. port setting: transmit enable = 0, receive enable = 0, learning disable = 0. software action: the processor should program the static mac table with the entries t hat it needs to receive (e.g., bpdu packets). the overriding bit should be set so that the switch will forward those specific packets to the processor. the processor may send packets to the port(s) in this state, see tail ta gging mode section for details. address learning is enabled on the port in this state. ports in forwarding states fully participate in both data forwarding and mac learning. forwarding state: packets are forwarded and received normally. learning is enabled. port setting: transmit enable = 1, receive enable = 1, learning disable = 0. software action: the processor should program the static mac table with the entries t hat it needs to receive (e.g., bpdu packets). the overriding bit should be set so that the switch will forward t hose specific packets to the processor. the processor may send packets to the port(s) in this state, see tail tagging mode section for details. address learning is enabled on the port in this state. rstp uses only one type of bpdu called rstp bpdus. they are similar to stp conf iguration bpdus with the exception o f a type field set to version 2 for rstp and version 0 for stp, and a flag field carrying additional information. tail tagging mode the tail tag is only seen and used by the port 3 interface, which should be connected to a processor. it is an effective way to retrieve the ingress port information for spanning tree protocol igmp snooping and other appli cations . the bit 1 and bit 0 in the one byte tail tagging is used to indicate the source/destination port in port 3. b it 3 and bit 2 are used for the priority setting of the ingress frame in port 3. other bits are not used. the tail tag feature is enable d by setting r egister 3 bit 6. figure 7 . tail tag frame format downloaded from: http:/// micrel, inc. ksz8873mll/fll/rll september 20, 2013 40 revision 1.6 table 13 . tail tag ru les ingress to port 3 (host - > ksz8873mll/fll/rll) bit [1,0] destination port 0,0 normal (address look up) 0,1 port 1 1,0 port 2 1,1 port 1 and 2 bit [3,2] frame priority 0,0 priority 0 0,1 priority 1 1,0 priority 2 1,1 priority 3 egress from port 3 (ksz8873mll/fll/rll - >host) bit [0] source port 0 port 1 1 port 2 igmp support for internet group management protocol (igmp) support in layer 2, the ksz8873mll/fll/rll pr ovides two components, igmp snooping and igmp send - back to the subscribed port. igmp snooping the ksz8873mll/fll/rll traps igmp packets and forwards them only to the processor (port 3). the ig mp packets are identified as ip packets (either ethernet ip packets, or ieee 802.3 s nap ip packets) with ip version = 0x4 and protocol ver sion number = 0x2. igmp send - back to the subscribed port once the host responds the received igmp packet, the host should knows the original igmp ingress port and send back the igmp packet to this port only , otherwise this igmp packet will be broadcasted t o all port to downgrade the performance. enable the tail tag mode, the host will know the igmp packet receive d port from tail tag bits [0] and can send back the response igmp packet to this subscribed port by setting the bits [1,0] in the t ail tag . enable tail tag mode by setting register 3 bit 6. the tail tag will be removed automatically when the igmp packet is sent out from the subscri bed port. port mirroring support ksz8873mll/fll/rll supports port mirroring comprehensively as: ? receive only mirror on a port ? all the packets received on the port are mirrored on the sniffer port. for example, port 1 is programmed to be receive sniff and port 3 is programmed to be the sniffer port. a packet received on port 1 is dest ined to port 2 after the internal lookup. the ksz8873mll/fll/rll forwards the packet to both port 2 and port 3. the ksz8873mll /fll/rll can optionally even forward bad received packets to the sniffer port. ? transmit only mirror on a port ? all the packets transmitted on the port are mirrored on the sniffer port. for example, port 1 is programmed to be transmit sniff and port 3 is programmed to be the sniffer port. a packet received on port 2 is destined to port 1 after the internal lookup. the ksz8873mll/fll/rll forwards the packet to both port 1 and port 3. ? receive and transmit mirror on two ports downloaded from: http:/// micrel, inc. ksz8873mll/fll/rll september 20, 2013 41 revision 1.6 ? all the packets received on port a and transmitted on port b are mirrored on the sniffer port. to turn on the and feature, set r egister 5 bit [0] to 1. for example, port 1 is programmed to be receive sniff , port 2 is programmed to be transmit sniff, and port 3 is programmed to be the sniffer port. a packet received on port 1 is destined to port 2 after the internal lookup. the ksz8873mll/fll/rll forwards the packet to both port 2 and port 3. multiple ports can be selected as receive sniff or transmit sniff. in addition, any port can be selected as the sniffer port. all these per port features can be selected through r egister s 17, 33, and 49 for ports 1, 2 and 3, respectively. rate limiting support the ksz8873mll/fll/rll provides a fine resolution hardware rate limiting from 64kbps to 99mbps . the rate step is 64kbps when the rate range is from 64kbps to 960kbps and 1mbps for 1mbps to 100mbps (100bt) or to 10mbps(10b t) (refer to data rate limit table). the rate limit is independently on the rece ive side and on the transmit side on a per port basis. for 10base - t, a rate setting above 10 mbps means the rate is not limited. on the receive side, the data receive rate for each priority at each port can be limited by setting up ingress rate control regis ters. on the transmit side, the data transmit rate for each priority queue at each port can be limited by setting up egress rate c ontrol registers. the size of each frame has options to include minimum ifg (inter frame gap) or preamble byte, in addition to the data field (from packet da to fcs). for ingress rate limiting, ksz8873mll/fll/rll provides options to selectively choose frames from all types, multicast, broadcast, and flooded unicast frames. the ksz8873mll/fll/rll counts the data rate from those selected type of frames. packets are dropped at the ingress port when the data rate exceeds the specified rate lim it. for egress rate limiting, the leaky bucket algorithm is applied to each output priority que ue for shaping output traffic. inter frame gap is stretched on a per frame base to generate smooth, non - burst egress traffic. the throughput of each output priority queue is limited by the egress rate specified. if any egress queue receives more traffic than the specified egress rate throughput, pac kets may be accumulated in the output queue and packet memory. after the memory of the queue or the port is used up, packet dropping or flow control will be triggered. as a result of congestion, the actual egress rate may be dominated by flow control/dropping at the ingress end, and may be therefore slightly less than the specified egress rate. to reduce congestion, it is a good practice to make sure the egress bandwidth exceeds the ingress bandwidt h. unicast mac address filtering the unicast mac address filtering function works in conjunction with th e static mac address table. first, the static mac address table is used to assign a dedicated mac address to a specific port. if a unicast mac address is not recorded in the static table, it is also not learned in the dynamic mac table. the ksz 8873mll/fll/rll is then configured with the option to either filter or forward unicast packets for an unknown mac address. this option is enabled and configured in r egister 14. this function is useful in preventing the broadcast of unicast packets that could degrade the quality of the p ort in applications such as voice over internet protocol (voip). configuration interface the ksz8873mll/fll/rll can operate as both a managed switch and an unmanaged switch. in unmanaged mode, the ksz8873mll/fll/rll is typically programmed using an eeprom . if no eeprom is present, the ksz8873mll/fll/rll is configured using its default register settings. some default s ettings are configured via strap - in pin options. the strap - in pins are indicated in the pin description and i/o assignment table. i 2 c master serial bus configuration with an additional i 2 c (2 - wire) eeprom, the ksz8873mll/fll/rll can perform more advanced switch features l ike broadcast storm protection and rate control without the need of an external processor. downloaded from: http:/// micrel, inc. ksz8873mll/fll/rll september 20, 2013 42 revision 1.6 for ksz8873mll/fll/rll i2c master configuration, the eeprom stores the configuration data for r egister 0 to r egister 120 (as defined in the ksz8873mll/fll/rll register map) with the exception of the read only st atus registers. after the de - assertion of reset, the ksz8873mll/fll/rll sequentially reads in the configuration data for all control registers, starting from r egister 0. .... .... .... rst_n scl sda t prgm <15 ms figure 8 . eeprom configuration timing diagram the following is a sample procedure for programming the ksz8873mll/fll/rll with a pre - configured eeprom: 1. connect the ksz8873mll/fll/rll to the eeprom by joining the scl and sda signals of the res pective devices. 2. enable i 2 c master mode by setting the ksz8873mll/fll/rll strap - in pins, p2led[1:0] to 00. 3. check to ensure that the ksz8873mll/fll/rll reset signal input, rstn, is properly connected to the external reset source at the board level. 4. program the desired configuration data into the eeprom. 5. place the eeprom on the board and power up the board. 6. assert an active - low reset to the rstn pin of the ksz8873mll/fll/rll. after reset is de - asserted, the ksz8873mll/fll/rll begins reading the configuration data from the eeprom. the k sz8873mll/fll/rll checks that the first byte read from the eeprom is 88. if this value is correct, eeprom c onfiguration continues. if not, eeprom configuration access is denied and all other data sent from the eeprom is ignored by the ksz8873mll/fll/rll. note : for proper operation, check to ensure that the ksz8873mll/fll/rll pwrdn i nput signal is not asserted during the reset operation. the pwrdn input is active low. i 2 c slave serial bus configuration in managed mode, the ksz8873mll/fll/rll can be configured as an i2c slave device. in this mode, an i2c master device (external controller/cpu) has complete programming access to the k sz8873mll/fll/rlls 198 registers. programming access includes the global registers, port registers, advanced contro l registers and indirect access to the static mac table, vlan table, dynamic mac table, and mib counters. the t ables and counte r s are indirectly accessed via registers 121 to 131. in i 2 c slave mode, the ksz8873mll/fll/rll operates like other i2c slave devices. addressing the ksz8873mll/fll/rlls 8 - bit registers is similar to addressing atmels at24c02 eeproms memory loc ations. details of i 2 c read/write operations and related timing information can be found in the at24c02 datasheet. downloaded from: http:/// micrel, inc. ksz8873mll/fll/rll september 20, 2013 43 revision 1.6 two fixed 8 - bit device addresses are used to address the ksz8873mll/fll/rll in i2c slave mode. one is for read; the other is for write. the addresses are as follow: 1011_1111 micrel, inc. ksz8873mll/fll/rll september 20, 2013 44 revision 1.6 the following is a sample procedure for programming the ksz8873mll/fll/rll using the spi bus: 1. at the board level, connect the ksz8873mll/fll/rll pins as illustrated in table 13 : table 14 . spi connections ksz8873mll/fll/rll pin number ksz8873mll/fll/rll signal name external processor signal description 40 spisn spi slave select 42 scl (spic) spi clock 43 sda (spid) spi data (master output; slave input) 39 spiq spi data (master input; slave output) 2. enable spi slave mode by setting the ksz8873mll/fll/rll strap - in p in s p2led[1:0] to 10. 3. power up the board and assert reset to the ksz8873mll/fll/rll. 4. configure the desired register settings in the ksz8873mll/fll/rll, using the spi write or mul tiple write command. 5. read back and verify the register settings in the ksz8873mll/fll/rll, using the spi read o r multiple read command. some of the configuration settings, such as aging enable, auto negotiation en able, force speed and power down can be programmed after the switch has been started. figure 9 through figure 12 illustrate the spi data cycles for write, read, multiple write and multip le read. the read data is registered out of spiq on the falling edge of spic, and the data input on spid is registered on the rising edge of spic. spiq spic spid spis_n 0 0 0 0 0 0 1 0 x a7 a6 a5 a4 a3 a2 a1 a0 write command write address write data d2 d0 d1 d3 d4 d5 d6 d7 figure 9 . spi write data cycle spiq spic spid spis_n 0 0 0 0 0 0 1 1 x a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 read command read address read data figure 10 . spi read data cycle downloaded from: http:/// micrel, inc. ksz8873mll/fll/rll september 20, 2013 45 revision 1.6 spiq spic spid spis_n 0 0 0 0 0 0 1 0 x a7 a6 a5 a4 a3 a2 a1 a0 write command write address byte 1 d2 d0 d1 d3 d4 d5 d6 d7 spiq spic spid spis_n d7 d6 d5 d4 d4 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 byte 2 byte 3 ... byte n d2 d0 d1 d3 d4 d5 d6 d7 figure 11 . spi multiple write spiq spic spid spis_n 0 0 0 0 0 0 1 1 x a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 read command read address byte 1 x x x x x x x x x x x x x x x x byte 2 byte 3 byte n x x x x x x x x x x x x x x x x d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 spiq spic spid spis_n figure 12 . spi multiple read downloaded from: http:/// micrel, inc. ksz8873mll/fll/rll september 20, 2013 46 revision 1.6 loopback support the ksz8873mll/fll/rll provides loopback support for remote diagnostic of failure. in loopbac k mode, the speed at both phy ports needs to be set to 100base - tx. two types of loopback are supported: far - end loopback and near - end (remote) loopback. far -e nd loopback far - end loopback is conducted between the ksz8873mll/fll/rlls two phy ports. the loopback is limited to a few packages at a time for diagnosis purpose and cannot support large traffic . the loopback path starts at the originating. phy ports receive inputs (rxp/rxm), wraps around at the loopback ph y ports pmd/pma, and ends at the originating phy ports transmit outputs (txp/txm). bit [0] of registers 29 and 45 is used to enable far - end loopback for ports 1 and 2, respectively. alternatively, the mii management register 0, bit [14] can be used to enable far - end loopback. the far - end loopback path is illustrated in figure 13 . pm d/pm a pcs m ac sw it c h m ac pcs pm d/pm a txp / txm rxp / rxm originating phy port loop back phy port figure 13 . far - end loopback path downloaded from: http:/// micrel, inc. ksz8873mll/fll/rll september 20, 2013 47 revision 1.6 near -e nd (remote) loopback near - end (remote) loopback is conducted at either phy port 1 or phy port 2.of the ksz8873mll/fll/rl l. the loopback path starts at the phy ports receive inputs (rxpx/rxmx), w raps around at the same phy ports pmd/pma, and ends at the phy ports transmit outputs (txpx/txmx). bit [1] of registers 26 and 42 is used to enable near - end loopback for ports 1 and 2, respectively. alternatively, the mii management register 31, bit [1] can be used to enable near - end loopback. the near - end loopback paths are illustra ted in figure 14 . txp 1 / txm 1 rxp 1 / rxm 1 rxp 2 / rxm 2 txp 2 / txm 2 ph y port 1 ph y port 2 pm d/pm a pcs m ac sw it c h m ac pcs pm d/pm a figure 14 . near - end (remote) loopback path downloaded from: http:/// micrel, inc. ksz8873mll/fll/rll september 20, 2013 48 revision 1.6 mii management (miim) registers the miim interface is used to access the mii phy registers defined in this section. the spi, i 2 c, and smi interfaces can also be used to access some of these registers. the latter three interfaces use a d ifferent mapping mechanism than the miim interface. the phyads by defaults are assigned 0x1 for phy1 (port 1) and 0x2 for phy2 (port 2). additionally, these phyads can be programmed to the phy addresses specified in bits[7:3] of register 15 (0x0f ): global control 13. the regad supported are 0x0 - 0x5, 0x1d and 0x1f. register number description phyad = 0x1, regad = 0x0 phy1 basic control register phyad = 0x1, regad = 0x1 phy1 basic status register phyad = 0x1, regad = 0x2 phy1 physical identifier i phyad = 0x1, regad = 0x3 phy1 physical identifier ii phyad = 0x1, regad = 0x4 phy1 auto - negotiation advertisement register phyad = 0x1, regad = 0x5 phy1 auto - negotiation link partner ability register phyad = 0x1, 0x6 C 0x1c phy1 not supported phyad = 0x1, 0x1d phy1 not supported phyad = 0x1, 0x1e phy1 not supported phyad = 0x1, 0x1f phy1 special control/status phyad = 0x2, regad = 0x0 phy2 basic control register phyad = 0x2, regad = 0x1 phy2 basic status register phyad = 0x2, regad = 0x2 phy2 physical identifier i phyad = 0x2, regad = 0x3 phy2 physical identifier ii phyad = 0x2, regad = 0x4 phy2 auto - negotiation advertisement register phyad = 0x2, regad = 0x5 phy2 auto - negotiation link partner ability register phyad = 0x2, 0x6 C 0x1c phy2 not supported phyad = 0x2, 0x1d phy2 linkmd control/status phyad = 0x2, 0x1e phy2 not supported phyad = 0x2, 0x1f phy2 special control/status downloaded from: http:/// micrel, inc. ksz8873mll/fll/rll september 20, 2013 49 revision 1.6 phy1 register 0 (phyad = 0x1, regad = 0x0): mii basic control phy2 register 0 (phyad = 0x2, regad = 0x0): mii basic control bit name r/w description default reference 15 soft reset ro not supported 0 14 loopback r/w =1, perform loopback, as indicated: port 1 loopback (reg. 29, bit 0 = 1) start: rxp2/rxm2 (port 2) loopback: pmd/pma of port 1s phy end: txp2/txm2 (port 2) port 2 loopback (reg. 45, bit 0 = 1) start: rxp1/rxm1 (port 1) loopback: pmd/pma of port 2s phy end: txp1/txm1 (port 1) =0, normal operation 0 reg. 29, bit 0 reg. 45, bit 0 13 force 100 r/w =1, 100 mbps =0, 10 mbps 0 reg. 28, bit 6 reg. 44, bit 6 12 an enable r/w =1, auto - negotiation enabled =0, auto - negotiation disabled 1 reg. 28, bit 7 reg. 44, bit 7 11 power down r/w =1, power down =0, normal operation 0 reg. 29, bit 3 reg. 45, bit 3 10 isolate ro not supported 0 9 restart an r/w =1, restart auto - negotiation =0, normal operation 0 reg. 29, bit 5 reg. 45, bit 5 8 force full duplex r/w =1, full duplex =0, half duplex 0 reg. 28, bit 5 reg. 44, bit 5 7 collision test ro not supported 0 6 reserved ro 0 5 hp_mdix r/w =1, hp auto mdi/mdi - x mode =0, micrel auto mdi/mdi - x mode 1 reg. 31, bit 7 reg. 47, bit 7 4 force mdi r/w =1, force mdi (transmit on rxp / rxm pins) =0, normal operation (transmit on txp / txm pins) 0 reg. 29, bit 1 reg. 45, bit 1 3 disable mdix r/w =1, disable auto mdi -x =0, enable auto mdi -x 0 reg. 29, bit 2 reg. 45, bit 2 2 disable far - end fault r/w =1, disable far - end fault detection =0, normal operation 0 reg. 29, bit 4 1 disable transmit r/w =1, disable transmit =0, normal operation 0 reg. 29, bit 6 reg. 45, bit 6 0 disable led r/w =1, disable led =0, normal operation 0 reg. 29, bit 7 reg. 45, bit 7 downloaded from: http:/// micrel, inc. ksz8873mll/fll/rll september 20, 2013 50 revision 1.6 phy1 register 1 (phyad = 0x1, regad = 0x1): mii basic status phy2 register 1 (phyad = 0x2, regad = 0x1): mii basic status bit name r/w description default reference 15 t4 capable ro =0, not 100 base - t4 capable 0 14 100 full capable ro =1, 100base - tx full duplex capable =0, not capable of 100base - tx full duplex 1 always 1 13 100 half capable ro =1, 100base - tx half duplex capable =0, not 100base - tx half duplex capable 1 always 1 12 10 full capable ro =1, 10base - t full duplex capable =0, not 10base - t full duplex capable 1 always 1 11 10 half capable ro =1, 10base - t half duplex capable =0, not 10base - t half duplex capable 1 always 1 10 -7 reserved ro 0000 6 preamble suppressed ro not supported 0 5 an complete ro =1, auto - negotiation complete =0, auto - negotiation not completed 0 reg. 30, bit 6 reg. 46, bit 6 4 far - end fault ro =1, far - end fault detected =0, no far - end fault detected 0 reg. 31, bit 0 3 an capable ro =1, auto - negotiation capable =0, not auto - negotiation capable 1 reg. 28, bit 7 reg. 44, bit 7 2 link status ro =1, link is up =0, link is down 0 reg. 30, bit 5 reg. 46, bit 5 1 jabber test ro not supported 0 0 extended capable ro =0, not extended register capable 0 phy1 register 2 (phyad = 0x1, regad = 0x2): phyid high phy2 register 2 (phyad = 0x2, regad = 0x2): phyid high bit name r/w description default 15 -0 phyid high ro high order phyid bits 0x0022 phy1 register 3 (phyad = 0x1, regad = 0x3): phyid low phy2 register 3 (phyad = 0x2, regad = 0x3): phyid low bit name r/w description default 15 -0 phyid low ro low order phyid bits 0x1430 downloaded from: http:/// micrel, inc. ksz8873mll/fll/rll september 20, 2013 51 revision 1.6 phy1 register 4 (phyad = 0x1, regad = 0x4): auto - negotiation advertisement ability phy2 register 4 (phyad = 0x2, regad = 0x4): auto - negotiation advertisement ability bit name r/w description default reference 15 next page ro not supported 0 14 reserved ro 0 13 remote fault ro not supported 0 12 - 11 reserved ro 00 10 pause r/w =1, advertise pause ability =0, do not advertise pause ability 1 reg. 28, bit 4 reg. 44, bit 4 9 reserved r/w 0 8 adv 100 full r/w =1, advertise 100 full duplex ability =0, do not advertise 100 full duplex ability 1 reg. 28, bit 3 reg. 44, bit 3 7 adv 100 half r/w =1, advertise 100 half duplex ability =0, do not advertise 100 half duplex ability 1 reg. 28, bit 2 reg. 44, bit 2 6 adv 10 full r/w =1, advertise 10 full duplex ability =0, do not advertise 10 full duplex ability 1 reg. 28, bit 1 reg. 44, bit 1 5 adv 10 half r/w =1, advertise 10 half duplex ability =0, do not advertise 10 half duplex ability 1 reg. 28, bit 0 reg. 44, bit 0 4-0 selector field ro 802.3 00001 phy1 register 5 (phyad = 0x1, regad = 0x5): auto - negotiation link partner ability phy2 register 5 (phyad = 0x2, regad = 0x5): auto - negotiation link partner ability bit name r/w description default reference 15 next page ro not supported 0 14 lp ack ro not supported 0 13 remote fault ro not supported 0 12 - 11 reserved ro 00 10 pause ro link partner pause capability 0 reg. 30, bit 4 reg. 46, bit 4 9 reserved ro 0 8 adv 100 full ro link partner 100 full capability 0 reg. 30, bit 3 reg. 46, bit 3 7 adv 100 half ro link partner 100 half capability 0 reg. 30, bit 2 reg. 46, bit 2 6 adv 10 full ro link partner 10 full capability 0 reg. 30, bit 1 reg. 46, bit 1 5 adv 10 half ro link partner 10 half capability 0 reg. 30, bit 0 reg. 46, bit 0 4-0 reserved ro 00000 downloaded from: http:/// micrel, inc. ksz8873mll/fll/rll september 20, 2013 52 revision 1.6 phy1 register 29 (phyad = 0x1, regad = 0x1d): not supported phy2 register 29 (phyad = 0x2, regad = 0x1d): linkmd control/status bit name r/w description default reference 15 vct_enable r/w (sc) =1, enable cable diagnostic. after vct test has completed, this bit will be self - cleared. =0, indicate cable diagnostic test (if enabled) has completed and the status information is valid for read. 0 reg. 42, bit 4 14 - 13 vct_result ro =00, normal condition =01, open condition detected in cable =10, short condition detected in cable =11, cable diagnostic test has failed 00 reg 42, bit[6:5] 12 vct 10m short ro =1, less than 10 meter short 0 reg. 42, bit 7 11 -9 reserved ro reserved 000 8-0 vct_fault_count ro distance to the fault. its approximately 0.4m*vct_fault_count[8:0] {0, (0x00)} {(reg. 42, bit 0), (reg. 43, bit[7:0])} phy1 register 31 (phyad = 0x1, regad = 0x1f): phy special control/status phy2 register 31 (phyad = 0x2, regad = 0x1f): phy special control/status bit name r/w description default reference 15 -6 reserved ro reserved {(0x00),00} 5 polrvs ro =1, polarity is reversed =0, polarity is not reversed 0 reg. 31, bit 5 reg. 47, bit 5 note: this bit is only valid for 10bt 4 mdi - x status ro =1, mdi =0, mdi -x 0 reg. 30, bit 7 reg. 46, bit 7 3 force_lnk r/w =1, force link pass =0, normal operation 0 reg. 26, bit 3 reg. 42, bit 3 2 pwrsave r/w =0, enable power saving =1, disable power saving 1 reg. 26, bit 2 reg. 42, bit 2 1 remote loopback r/w =1, perform remote loopback, as follows: port 1 (reg. 26, bit 1 = 1) start: rxp1/rxm1 (port 1) loopback: pmd/pma of port 1s phy end: txp1/txm1 (port 1) port 2 (reg. 42, bit 1 = 1) start: rxp2/rxm2 (port 2) loopback: pmd/pma of port 2s phy end: txp2/txm2 (port 2) =0, normal operation 0 reg. 26, bit 1 reg. 42, bit 1 0 reserved r/w reserved do not change the default value. 0 downloaded from: http:/// micrel, inc. ksz8873mll/fll/rll september 20, 2013 53 revision 1.6 memory map (8-b it registers) global registers register (decimal) register (hex) description 0-1 0x00 - 0x01 chip id registers 2- 15 0x02 - 0x0f global control registers p ort registers register (decimal) register (hex) description 16 - 29 0x10 - 0x1d port 1 control registers, including mii phy registers 30 - 31 0x1e - 0x1f port 1 status registers, including mii phy registers 32 - 45 0x20 - 0x2d port 2 control registers, including mii phy registers 46 - 47 0x2e - 0x2f port 2 status registers, including mii phy registers 48 - 57 0x30 - 0x39 port 3 control registers 58 - 62 0x3a - 0x3e reserved 63 0x3f port 3 status register 64 - 95 0x40 - 0x5f reserved advanced control registers register (decimal) register (hex) description 96 - 111 0x60 - 0x6f tos priority control registers 112 - 117 0x70 - 0x75 switch engines mac address registers 118 - 120 0x76 - 0x78 user defined registers 121 - 122 0x79 - 0x7a indirect access control registers 123 - 131 0x7b - 0x83 indirect data registers 142 - 153 0x8e - 0x99 station address 154 - 165 0x9a - 0xa5 egress data rate limit 166 0xa6 device mode indicator 167 - 170 0xa7 - 0xaa high - priority packet buffer reserved 171 - 174 0xab - 0xae pm usage flow control select mode 175 - 186 0xaf - 0xba txq split 187 - 188 0xbb - 0xbc link change interrupt register 189 0xbd force pause off iteration limit enable 192 0xc0 fiber signal threshold 194 0xc2 insert src pvid 195 0xc3 power management and led mode 196 0xc4 sleep mode 198 0xc6 forward invalid vid frame and host mode downloaded from: http:/// micrel, inc. ksz8873mll/fll/rll september 20, 2013 54 revision 1.6 register description global registers (registers 0 C 15) register 0 (0x00): chip id0 bit name r/w description default 7-0 family id ro chip family 0x88 register 1 (0x01): chip id1 / start switch bit name r/w description default 7-4 chip id ro 0x 3 is assigned to m series. ( 7 3m) 0x 3 3-1 revision id ro revision id - 0 start switch rw = 1, start the switch (default) 0=, stop the switch 1 register 2 (0x02): global control 0 bit name r/w description default 7 new back - off enable r/w new back - off algorithm designed for unh =1, enable =0, disable 0 6 rserved ro rserved 0 5 flush dynamic mac table r/w =1, e nable f lush dynamic mac table for spanning tree application =0, disable 0 4 flush static mac table r/w =1, enable f lush static mac table for spanning tree application =0, disable 0 3 pass flow control packet r/w =1, switch will pass 802.1x flow control packets =0, s witch will drop 802.1x flow control packets 0 2 reserved ro reserved do not change the default value. 0 1 reserved ro reserved do not change the default value. 0 0 re served ro rserved 0 downloaded from: http:/// micrel, inc. ksz8873mll/fll/rll september 20, 2013 55 revision 1.6 register 3 (0x03): global control 1 bit name r/w description default 7 pass all frames r/w =1, switch all packets including bad ones. used solely for debugging purposes. works in conjunction with sniffer mode only. 0 6 port 3 tail tag mode enable r/w =1, enable port 3 tail tag mode. =0, disable. 0 5 ieee 802.3x transmit direction flow control enable r/w =1, will enable transmit direction flow control feature. =0, will not enable transmit direction flow control feature. switch will not generate any flow control (pause) frame. 1 4 ieee 802.3x receive direction flow control enable r/w =1, will enable receive direction flow control feature. =0, will not enable receive direction flow control feature. switch will not react to any flow control (pause) frame it receives. 1 3 frame length field check r/w =1, will check frame length field in the ieee packets. if the actual length does not match, the packet will be dropped (for length/type field < 1500). =0, not check 0 2 aging enable r/w =1, enable age function in the chip =0, disable age function in the chip 1 1 fast age enable r/w =1, turn on fast age (800us) 0 0 aggressive back-o ff enable r/w =1, enable more aggressive back off algorithm in half duplex mode to enhance performance. this is not an ieee standard. 0 register 4 (0x04): global control 2 bit name r/w description default 7 unicast port-vlan mismatch discard r/w this feature is used with port - vlan (described in reg. 17, reg. 33, ) =1, all packets can not cross vlan boundary =0, unicast packets (excluding unkown/multicast/ broadcast) can cross vlan boundary note: port mirroring is not supported if this bit is set to 0. 1 6 multicast storm protection disable r/w =1, broadcast storm protection does not include multicast packets. only da = ff - ff - ff - ff - ff - ff packets will be regulated. =0, broadcast storm protection includes da = ff - ff - ff - ff - ff - ff and da[40] = 1 packets. 1 5 back pressure mode r/w =1, carrier sense based backpressure is selected =0, collision based backpressure is selected 1 4 flow control and back pressure fair mode r/w =1, fair mode is selected. in this mode, if a flow control port and a non - flow control port talk to the same destination port, packets from the non - flow control port may be dropped. this is to prevent the flow control port from being flow controlled for an extended period of time. =0, in this mode, if a flow control port and a non - flow control port talk to the same destination port, the flow control port will be flow controlled. this may not be fair to the flow control port. 1 3 no excessive collision drop r/w =1, the switch will not drop packets when 16 or more collisions occur. =0, the switch will drop packets when 16 or more collisions occur. 0 downloaded from: http:/// micrel, inc. ksz8873mll/fll/rll september 20, 2013 56 revision 1.6 register 4 (0x04): global control 2 (continued) bit name r/w description default 2 huge packet support r/w =1, will accept packet sizes up to 1916 bytes (inclusive). this bit setting wil l override setting from bit 1 of this register. =0, the max packet size will be determined by bit 1 of this register. 0 1 legal maximum packet size ch eck enable r/w =0, will accept packet sizes up to 1536 bytes (inclusive). =1, 1522 bytes for tagged packets, 1518 bytes for untagged packets. any packets larger than the specified value will be dropped. 0 0 reserved r/w reserved do not change the default value. 0 register 5 (0x05): global control 3 bit name r/w description default 7 802.1q vlan enable r/w =1, 802.1q vlan mode is turned on. vlan table needs to set up before the operation. =0, 802.1q vlan is disabled. 0 6 igmp snoop enable on switch mii interface r/w =1, igmp snoop is enabled. all igmp packets will be forwarded to the switch mii port. =0, igmp snoop is disabled. 0 5 reserved ro reserved do not change the default values. 0 4 reserved ro reserved do not change the default values. 0 3 weighted fair queue enable r/w =0, p riority method set by the registers 175 - 186 bit [7]=0 for port 1, port 2 and port 3. =1, weighted fair queueing enabled. when all four queues have packets waiting to transmit, the bandwidth allocation is q3:q2:q1:q0 = 8 :4:2:1. if any queues are empty, the highest non - empty queue gets one more weighting. for example, if q2 is empty, q3:q2:q1:q0 becomes (8+1):0:2:1. 0 2 reserved ro reserved do not change the default values. 0 1 reserved ro reserved do not change the default values. 0 0 sniff mode select r/w =1, will do rx and tx sniff (both source port and destination port need to match) =0, will do rx or tx sniff (either source port or destination port needs to match). this is the mode used to implement rx only sniff. 0 downloaded from: http:/// micrel, inc. ksz8873mll/fll/rll september 20, 2013 57 revision 1.6 register 6 (0x06): global control 4 bit name r/w description default 7 reserved ro reserved do not change the default values. 0 6 port 3 duplex mode selection r/w =1, enable port 3 mii to half - duplex mode. =0, enable port 3 mii to full - duplex mode. 0 pin p1led0 strap option. pull- up (1): half - duplex mode pull- down (0): full - duplex mode (default) note: p1led0 has internal pull - down . 5 port 3 flow control enable r/w =1, enable full duplex flow control on switch port 3 mii interface. =0, disable full duplex flow control on switch port 3 mii interface. 1 pin p1led1 strap option. pull- up(1): enable flow control pull- down(0): disable flow control note: p1led1 has internal pull - up . 4 port 3 speed selection r/w =1, the port 3 mii switch interface is in 10mbps mode =0, the port 3 mii switch interface is in 100mbps mode 0 pin p3spd strap option. pull- up (1 ): enable 10mbps pull- down (0 ): enable 10 0 mbps (default) note: p3spd has internal pull - down . 3 null vid replacement r/w =1, will replace null vid with port vid (12 bits) =0, no replacement for null vid 0 2-0 broadcast storm protection rate (1) bit [10:8] r/w this register along with the next register determines how many 64 byte blocks of packet data are allowed on an input port in a preset period. the period is 67ms for 100bt or 500ms for 10bt. the default is 1%. 000 register 7 (0x07): global control 5 bit name r/w description default 7-0 broadcast storm protection rate ( 3 ) bit [7:0] r/w this register along with the previous register determines how many 64 byte blocks of packet data are allowed on an input port in a preset period. the period is 67ms for 100bt or 500ms for 10bt. the default is 1%. 0x63 note: 3. 100bt rate: 148,800 frames/sec * 67 ms/interval * 1% = 99 frames/interval (approx.) = 0x63 . downloaded from: http:/// micrel, inc. ksz8873mll/fll/rll september 20, 2013 58 revision 1.6 register 8 (0x08): global control 6 bit name r/w description default 7-0 factory testing ro reserved do not change the default values. 0x00 register 9 (0x09): global control 7 bit name r/w description default 7-0 factory testing ro reserved do not change the default values. 0x24 register 10 (0x0a): global control 8 bit name r/w description default 7-0 factory testing ro reserved do not change the default values. 0x35 register 11 (0x0b): global control 9 bit name r/w description default 7-6 cpu interface clock selection r/w =00, 31.25 mhz supports spi speed below 6mhz =01, 62.5mhz supports spi speed between 6mhz to 12.5mhz =10, 125mhz supports spi speed above 12.5mhz note: lower clock speed will save more power consumption, it is better set to to 31.25mhz if spi doesn t request a high speed. 10 5-4 reserved ro n/a don t change 00 3-2 reserved ro n/a don t change 10 1 reserved ro n/a don t change 0 0 reserved ro n/a don t change 0 register 12 (0x0c): global control 10 bit name r/w description default 7-6 tag_0x3 r/w ieee 802.1p mapping. the value in this field is used as the frames priority when its ieee 802.1p tag has a value of 0x3. 01 5-4 tag_0x2 r/w ieee 802.1p mapping. the value in this field is used as the frames priority when its ieee 802.1p tag has a value of 0x2. 01 3-2 tag_0x1 r/w ieee 802.1p mapping. the value in this field is used as the frames priority when its ieee 802.1p tag has a value of 0x1. 00 1-0 tag_0x0 r/w ieee 802.1p mapping. the value in this field is used as the frames priority when its ieee 802.1p tag has a value of 0x0. 00 downloaded from: http:/// micrel, inc. ksz8873mll/fll/rll september 20, 2013 59 revision 1.6 register 13 (0x0d): global control 11 bit name r/w description default 7-6 tag_0x7 r/w ieee 802.1p mapping. the value in this field is used as the frames priority when its ieee 802.1p tag has a value of 0x7. 11 5-4 tag_0x6 r/w ieee 802.1p mapping. the value in this field is used as the frames priority when its ieee 802.1p tag has a value of 0x6. 11 3-2 tag_0x5 r/w ieee 802.1p mapping. the value in this field is used as the frames priority when its ieee 802.1p tag has a value of 0x5. 10 1-0 tag_0x4 r/w ieee 802.1p mapping. the value in this field is used as the frames priority when its ieee 802.1p tag has a value of 0x4. 10 register 14 (0x0e): global control 12 bit name r/w description default 7 unknown packet default port enable r/w send packets with unknown destination mac addresses to specified port(s) in bits [2:0] of this register. =0, disable =1, enable 0 6 drive strength of i/o pad r/w =1, 16ma =0, 8ma 1 5 reserved r/w reserved do not change the default values. 0 4 reserved ro reserved 0 3 reserved r/w reserved do not change the default values. 0 2-0 unknown packet default port r/w specify which port(s) to send packets with unknown destination mac addresses. this feature is enabled by bit [7] of this register. bit 2 stands for port 3. bit 1 stands for port 2. bit 0 stands for port 1. an 1 includes a port. an 0 excludes a port. 111 downloaded from: http:/// micrel, inc. ksz8873mll/fll/rll september 20, 2013 60 revision 1.6 register 15 (0x0f): global control 13 bit name r/w description default 7-3 phy address r/w 00000 : n/a 00001 : port 1 phy address is 0x1 00010 : port 1 phy address is 0x2 11101 : port 1 phy address is 0x29 11110 : n/a 11111 : n/a note: port 2 phy address = (port 1 phy address) + 1 00001 2-0 reserved ro reserved do not change the default values. 000 port registers (registers 16 C 95) the following registers are used to enable features that are assigned on a per port basis. the register bi t assignments are the same for all ports, but the address for each port is different, as indicated. register 16 (0x10): port 1 control 0 register 32 ( 0x20): port 2 control 0 register 48 (0x30): port 3 control 0 bit name r/w description default 7 broadcast storm protection enable r/w =1, enable broadcast storm protection for ingress packets on port =0, disable broadcast storm protection 0 6 diffserv priority classification enable r/w =1, enable diffserv priority classification for ingress packets (ipv4) on port =0, disable diffserv function 0 5 802.1p priority classification enable r/w =1, enable 802.1p priority classification for ingress packets on port =0, disable 802.1p 0 downloaded from: http:/// micrel, inc. ksz8873mll/fll/rll september 20, 2013 61 revision 1.6 register 16 (0x10): port 1 control 0 register 32 (0x20): port 2 control 0 register 48 (0x30): port 3 control 0 (continued) bit name r/w description default 4-3 port-b ased priority classification r/w =00, ingress packets on port will be classified as priority 0 queue if diffserv or 802.1p classification is not enabled or fails to classify. =01, ingress packets on port will be classified as priority 1 queue if diffserv or 802.1p classification is not enabled or fails to c lassify. =10, ingress packets on port will be classified as priority 2 queue if diffserv or 802.1p classification is not enabled or fails to classify. =11, ingress packets on port will be classified as priority 3 queue if diffserv or 802.1p classification is not enabled or fails to classify. note: diffserv, 802.1p and port priority can be enabled at the same time. the ored result of 802.1p and dscp overwrites the port priority. 00 2 tag insertion r/w =1, when packets are output on the port, the switch will add 802.1p/q tags to packets without 802.1p/q tags when received. the switch will not add tags to packets already tagged. the tag inserted is the ingress ports port vid. =0, disable tag insertion note: for the tag insertion availab le, the register 194 bits [5 - 0] have to be set first. 0 1 tag removal r/w =1, when packets are output on the port, the switch will remove 802.1p/q tags from packets with 802.1p/q tags when received. the switch will not modify packets received without tags. =0, disable tag removal 0 0 txq split enable r/w =1, split txq to 4 queue configuration. it cannot be enable at the same time with split 2 queue at register 18, 34,50 bit 7. =0, no split, treated as 1 queue configuration 0 downloaded from: http:/// micrel, inc. ksz8873mll/fll/rll september 20, 2013 62 revision 1.6 register 17 (0x11): port 1 control 1 register 33 (0x21): port 2 control 1 register 49 (0x31): port 3 control 1 bit name r/w description default 7 sniffer port r/w =1, port is designated as sniffer port and will transmit packets that are monitored. =0, port is a normal port 0 6 receive sniff r/w =1, all packets received on the port will be marked as monitored packets and forwarded to the designated sniffer port =0, no receive monitoring 0 5 transmit sniff r/w =1, all packets transmitted on the port will be marked as monitored packets and forwarded to the designated sniffer port =0, no transmit monitoring 0 4 double tag r/w =1, all packets will be tagged with port default tag of ingress port regardless of the original packets are tagged or not =0, do not double tagged on all packets 0 3 user priority ceiling r/w =1, if the packets user priority field is greater than the user priority fiel d in the port default tag register, replace the packets user priority field with the user priority field in the port default tag register. =0, do not compare and replace the packets user priority field 0 2-0 port vlan membership r/w define the ports egress port vlan membership. the port can only communicate within the membership. bit 2 stands for port 3, bit 1 stands for port 2, bit 0 stands for port 1. an 1 includes a port in the membership. an 0 excludes a port from membership. 111 register 18 (0x12): port 1 control 2 register 34 (0x22): port 2 control 2 register 50 (0x32): port 3 control 2 bit ( 4 ) name r/w description default 7 enable 2 queue split of tx queue r/w =1, enable it cannot be enable d at the same time with split 4 queue at register 16 , 32 , and 48 bit 0. =0, disable 0 6 ingress vlan filtering r/w =1,the switch will discard packets whose vid port membership in vlan table bits [18:16] does not include the ingress port. =0, no ingress vlan filtering. 0 5 discard non pvid packets r/w =1, the switch will discard packets whose vid does not match ingress port default vid. =0, no packets will be discarded 0 downloaded from: http:/// micrel, inc. ksz8873mll/fll/rll september 20, 2013 63 revision 1.6 register 18 (0x12): port 1 control 2 register 34 (0x22): port 2 control 2 register 50 (0x32): port 3 control 2 (continued) bit ( 4 ) name r/w description default 4 force flow control r/w =1, will always enable full duplex flow control on the port, regardless of an result. =0, full duplex flow control is enabled based on an result. pin value during reset: for port 1, p1ffc pin for port 2, smrxd30 pin for port 3, this bit has no meaning. flow control is set by reg. 6 bit 5. 3 back pressure enable r/w =1, enable ports half duplex back pressure =0, disable ports half duplex back pressure 0 2 transmit enable r/w =1, enable packet transmission on the port =0, disable packet transmission on the port 1 1 receive enable r/w =1, enable packet reception on the port =0, disable packet reception on the port 1 0 learning disable r/w =1, disable switch address learning capability =0, enable switch address learning 0 note: 4. bits [2:0] are used for spanning tree support. downloaded from: http:/// micrel, inc. ksz8873mll/fll/rll september 20, 2013 64 revision 1.6 register 19 ( 5 ) (0x13): port 1 control 3 register 35 (0x23): port 2 control 3 register 51 (0x33): port 3 control 3 bit name r/w description default 7-0 default tag [15:8] r/w ports default tag, containing 7- 5 : user priority bits 4 : cfi bit 3- 0 : vid[11:8] 0x00 register 20 ( 5 ) (0x14): port 1 control 4 register 36 (0x24): port 2 control 4 regist er 52 (0x34): port 3 control 4 bit name r/w description default 7-0 default tag [7:0] r/w ports default tag, containing 7-0 : vid[7:0] 0x0 1 note: 5. registers 19 and 20 (and those corresponding to other ports) serve two purposes: a. associated with the ingress untagged packets, and used for egress tagging. b. default vid for the ingress untagged or null - vid - tagged packets, and used for address lookup. register 21 (0x15): port 1 control 5 register 37 (0x25): port 2 control 5 register 53 (0x35): port 3 contr ol 5 bit name r/w description default 7 port 3 mii m ode selection r/w =1 , port 3 mii mac mode =0, port 3 mii phy mode note: bit 7 is reserved in the port 1 and port 2 of the port register control 5. but request to set the register 21 port 1 control 5 bit [7] = 1 for better emi, because this bit 7 of the register 21 is for port 1 mii of the mml part. in the mll/fll/rll parts, setting this bit will disable the unused internal 25mhz clock for the unused port 1 mii phy mode circuits. inversion of power strapped value of smrxdv3. 6 self- address filtering e nable maca1 (not for 0x35) r/w =1, enable port 1 s elf - address filtering maca1 =0, disable 0 downloaded from: http:/// micrel, inc. ksz8873mll/fll/rll september 20, 2013 65 revision 1.6 register 21 (0x15): port 1 control 5 register 37 (0x25): port 2 control 5 register 53 (0x35): port 3 control 5 (continued) bit name r/w description default 5 self- address filtering e nable maca2 (not for 0x35) r/w =1, enable port 2 self - address filtering maca 2 =0, disable 0 4 drop ingress tagged frame r/w =1, enable =0, disable 0 3-2 limit mode r/w ingress limit mode these bits determine what kinds of frames are limited and counted against ingress rate limiting. =00, limit and count all frames =01, limit and count broadcast, multicast, and flooded unicast frames =10, limit and count broadcast and multicast frames only =11, limit and count broadcast frames only 00 1 count ifg r/w count ifg b ytes =1, each frames minimum inter frame gap (ifg) bytes (12 per frame) are included in ingress and egress rate limiting calculations. =0, ifg bytes are not counted. 0 0 count pre r/w count preamble b ytes =1, each frames preamble bytes (8 per frame) are included in ingress and egress rate limiting calculations. =0, preamble bytes are not counted. 0 register 22[6:0] (0x16): port 1 q0 ingress data rate l imit register 38[6:0] (0x26): port 2 q0 ingress data rate l imit register 54[6:0] (0x36): port 3 q0 ingress data rate l imit bit name r/w description default 7 rmii refclk invert r/w =1, port 3 inverted refclk selected =0, port 3 original refclk selected note: bit 7 is available on port 3 in the rll device. other ports and devices will be reserved for this bit. 0 note: not applied to r eg. 38(port 2) 6-0 q0 ingress data rate limit r/w ingress data rate limit for priority 0 frames ingress traffic from this priority queue is shaped according to the ingress data rate limit table. 0 downloaded from: http:/// micrel, inc. ksz8873mll/fll/rll september 20, 2013 66 revision 1.6 regi ster 23[6:0] (0x17): port 1 q1 ingress data rate l imit register 39[6:0] (0x27): port 2 q1 ingress data rate l imit register 55[6:0] (0x37): port 3 q1 ingress data rate l imit bit name r/w description default 7 reserved r/w reserved do not change the default values. 0 6-0 q1 ingress data rate l imit r/w ingress data rate limit for priority 1 frames ingress traffic from this priority queue is shaped according to the ingress data rate limit table. 0 register 24[6:0] (0x18): port 1 q2 ingress data rate l imit register 40[6:0] (0x28): port 2 q2 ingress data rate l imit register 56[6:0] (0x38): port 3 q2 ingress data rate l imit bit name r/w description default 7 reserved ro reserved do not change the default values. 0 6-0 q2 ingress data rate l imit r/w ingress data rate limit for priority 2 frames ingress traffic from this priority queue is shaped according to ingress data rate limit table. 0 register 25[6:0] (0x19): port 1 q3 ingress data rate l imit register 41[6:0] (0x29): port 2 q3 ingress data rate l imit register 57[6:0] (0x39): port 3 q3 ingress data rate l imit bit name r/w description default 7 reserved ro reserved do not change the default values. 0 6-0 q3 ingress data rate l imit r/w ingress data rate limit for priority 3 frames ingress traffic from this priority queue is shaped according to ingress data rate limit table. 0 note: most of the contents in registers 26 - 31 and registers 42 - 47 for ports 1 and 2, respectively, can also be accessed with the miim phy registers. downloaded from: http:/// micrel, inc. ksz8873mll/fll/rll september 20, 2013 67 revision 1.6 table 15 . data rate limit table data rate limit for ingress or e gress 100bt register bit [6:0], q= 0..3 10bt register bit [6:0], q=0..3 1 to 0x63 for the rate 1 mbps to 99 mbps . 1 to 0x09 for the rate 1 mbps to 9 mbps 0 or 0x64 for the rate 100mbps 0 or 0x0a for the rate 10mbps 64 kbps 0x65 128 kbps 0x66 192 kbps 0x67 256 kbps 0x68 320 kbps 0x69 384 kbps 0x6a 448 kbps 0x6b 512 kbps 0x6c 576 kbps 0x6d 640 kbps 0x6e 704 kbps 0x6f 768 kbps 0x70 832 kbps 0x71 896 kbps 0x72 960 kbps 0x73 downloaded from: http:/// micrel, inc. ksz8873mll/fll/rll september 20, 2013 68 revision 1.6 register 26 (0x1a): port 1 phy special control/status register 42 (0x2a): port 2 phy special control/status register 58 (0x3a): reserved, not applied to p ort 3 bit name r/w description default 7 vct 10m short ro = 1, less than 10 meter short 0 6-5 vct_result ro = 00, normal condition = 01, open condition detected in cable = 10, short condition detected in cable = 11, cable diagnostic test has failed 00 4 vct_en r/w (sc) = 1, enable cable diagnostic test. after vct test has completed, this bit will be self - cleared. = 0, indicate cable diagnostic test (if enabled) has completed and the status information is valid for read. 0 3 force_lnk r/w = 1, force link pass = 0, normal operation 0 2 reserved ro reserved do not change the default value. 0 1 remote loopback r/w = 1, perform remote loopback, as follows: port 1 (reg. 26, bit 1 = 1) start: rxp1/rxm1 (port 1) loopback: pmd/pma of port 1s phy end: txp1/txm1 (port 1) port 2 (reg. 42, bit 1 = 1) start: rxp2/rxm2 (port 2) loopback: pmd/pma of port 2s phy end: txp2/txm2 (port 2) = 0, normal operation 0 0 vct_fault_count[8] ro bit[8] of vct fault count distance to the fault. its approximately 0.4m*vct_fault_count[8:0] 0 register 27 (0x1b): port 1 not support register 43 (0x2b): linkmd result register 59 (0x3b): reserved, not applied to p ort 3 bit name r/w description default 7-0 vct_fault_count[7:0] ro bits[7:0] of vct fault count distance to the fault. its approximately 0.4m*vct_fault_count[8:0] 0x00 downloaded from: http:/// micrel, inc. ksz8873mll/fll/rll september 20, 2013 69 revision 1.6 register 28 (0x1c): port 1 control 12 register 44 (0x2c): port 2 control 12 register 60 (0x3c): reserved, not applied to p ort 3 bit name r/w description default 7 auto negotiation enable r/w =1, auto negotiation is on =0, disable auto negotiation; speed and duplex are determined by bits 6 and 5 of this register. 1 for port 1, p1anen pin value during reset. for port 2, smrxd33 pin value during reset 6 force speed r/w =1, forced 100bt if an is disabled (bit 7) =0, forced 10bt if an is disabled (bit 7) 1 for port 1, p1spd pin value during reset. for port 2, smrxd32 pin value during reset. 5 force duplex r/w =1, forced full duplex if (1) an is disabled or (2) an is enabled but failed. =0, forced half duplex if (1) an is disabled or (2) an is enabled but failed. note: t his bit or strap pin should be set to 0 for the correct duplex mode indication of led and register status when the link - up is an to force mode. 1 for port 1, p1dpx pin value during reset. for port 2, smrxd31 pin value during reset. 4 advertise flow control capability r/w =1, advertise flow control (pause) capability =0, s uppress flow control (pause) capability from transmission to link partner 1 3 advertise 100bt full duplex capability r/w =1, advertise 100bt full duplex capability =0, suppress 100bt full duplex capability from transmission to link partner 1 2 advertise 100bt half duplex capability r/w =1, advertise 100bt half - duplex capability =0, suppress 100bt half - duplex capability from transmission to link partner 1 1 advertise 10bt full duplex capability r/w =1, advertise 10bt full duplex capability =0, suppress 10bt full duplex capability from transmission to link partner 1 0 advertise 10bt half duplex capability r/w =1, advertise 10bt half - duplex capability =0, suppress 10bt half - duplex capability from transmission to link partner 1 downloaded from: http:/// micrel, inc. ksz8873mll/fll/rll september 20, 2013 70 revision 1.6 register 29 (0x1d): port 1 control 13 register 45 (0x2d): port 2 control 13 register 61 (0x3d): reserved, not applied to p ort 3 bit name r/w description default 7 led off r/w =1, turn off all ports leds (ledx_1, ledx_0, where x is the port number). these pins will be driven high if this bit is set to one. =0, normal operation 0 6 txdis r/w =1, disable the ports transmitter =0, normal operation 0 5 restart an r/w =1, restart auto - negotiation =0, normal operation 0 4 disable far - end fault r/w =1, disable far - end fault detection and pattern transmission. =0, enable far - end fault detection and pattern transmission 0 3 power down r/w =1, power down =0, normal operation 0 2 disable auto mdi/mdi -x r/w =1, disable auto mdi/mdi - x function =0, enable auto mdi/mdi - x function 0 1 force mdi r/w if auto mdi/mdi - x is disabled, =1, force phy into mdi mode (transmit on rxp/rxm pins) =0, force phy into mdi - x mode (transmit on txp/txm pins) 0 0 loopback r/w =1, perform loopback, as indicated: port 1 loopback (reg. 29, bit 0 = 1) start: rxp2/rxm2 (port 2) loopback: pmd/pma of port 1s phy end: txp2/txm2 (port 2) port 2 loopback (reg. 45, bit 0 = 1) start: rxp1/rxm1 (port 1) loopback: pmd/pma of port 2s phy end: txp1/txm1 (port 1) =0, normal operation 0 downloaded from: http:/// micrel, inc. ksz8873mll/fll/rll september 20, 2013 71 revision 1.6 register 30 (0x1e): port 1 status 0 register 46 (0x2e): port 2 status 0 register 62 (0x3e): reserved, not applied to p ort 3 bit name r/w description default 7 mdi - x status ro =1, mdi =0, mdi -x 0 6 an done ro =1, auto - negotiation completed =0, auto - negotiation not completed 0 5 link good ro =1, link good =0, link not good 0 4 partner flow control capability ro =1, link partner flow control (pause) capable =0, link partner not flow control (pause) capable 0 3 partner 100bt full duplex capability ro =1, link partner 100bt full duplex capable =0, link partner not 100bt full duplex capable 0 2 partner 100bt half duplex capability ro =1, link partner 100bt half duplex capable =0, link partner not 100bt half duplex capable 0 1 partner 10bt full duplex capability ro =1, link partner 10bt full duplex capable =0, link partner not 10bt full duplex capable 0 0 partner 10bt half duplex capability ro =1, link partner 10bt half duplex capable =0, link partner not 10bt half duplex capable 0 downloaded from: http:/// micrel, inc. ksz8873mll/fll/rll september 20, 2013 72 revision 1.6 register 31 (0x1f): port 1 status 1 register 47 (0x2f): port 2 status 1 register 63 (0x3f): port 3 status 1 bit name r/w description default 7 hp_mdix r/w =1, hp auto mdi/mdi - x mode =0, micrel auto mdi/mdi - x mode 1 note: only ports 1 and 2 are phy ports. this bit is not applicable to port 3 (mii). 6 reserved ro reserved do not change the default value. 0 5 polrvs ro =1, polarity is reversed =0, polarity is not reversed 0 note: this bit is not applicable to port 3 (mii). this bit is only valid for 10bt 4 transmit flow control enable ro =1, transmit flow control feature is active =0, transmit flow control feature is inactive 0 3 receive flow control enable ro =1, receive flow control feature is active =0, receive flow control feature is inactive 0 2 operation speed ro =1, link speed is 100mbps =0, link speed is 10mbps 0 1 operation duplex ro =1, link duplex is full =0, link duplex is half 0 0 far - end fault ro =1, far - end fault status detected =0, no far - end fault status detected 0 this bit is applicable to port 1 only. register 67 (0x43): reset bit name r/w description default 4 software reset r/w =1, software reset =0, clear note: software reset will reset all registers to the initial values of the power - on reset or warm reset (keep the strap values). 0 0 pcs reset r/w =1, pcs reset is used when is doing software reset for a compelete reset =0, clear note: pcs reset will reset the state machine and clock domain in phy s pcs layer. 0 downloaded from: http:/// micrel, inc. ksz8873mll/fll/rll september 20, 2013 73 revision 1.6 advanced control registers (registers 96 -1 98 ) the ipv4 /ipv6 type - of -s ervice (to s) priority control registers implement a fully decoded, 128 - bit differentiated services code point (dscp ) register set that is used to determine priority from the tos field in the ip header. the most signific ant 6 bits of the tos field are fully decoded into 64 possibilities, and the singul ar code that results is compared against the corresponding bits in the dscp register to determine the priority. register 96 (0x60): tos priority control register 0 bit name r/w description default 7-6 dscp[7:6] r/w the value in this field is used as the frames priority when bits [7:2] of the frames ip tos/diffserv/traffic class value is 0x0 3. 00 5-4 dscp[5:4] r/w the value in this field is used as the frames priority when bits [7:2] of the frames ip tos/diffserv /traffic class value is 0x0 2. 00 3-2 dscp[3:2] r/w the value in this field is used as the frames priority when bits [7:2] of the frames ip tos/diffserv/traffic class value is 0x0 1. 00 1-0 dscp[1:0] r/w the value in this field is used as the frames priority when bits [7:2] of the frames ip tos/diffserv/traffic class value is 0x00. 00 register 97 (0x61): tos priority control register 1 bit name r/w description default 7-6 dscp[15:14] r/w the value in this field is used as the frames priority when bits [7:2] of the frames ip tos/diffserv/traffic class value is 0x 07 . 00 5-4 dscp[13:12] r/w the value in this field is used as the frames priority when bits [7:2] of the frames ip tos/diffserv/traffic class value is 0x 06 . 00 3-2 dscp[11:10] r/w the value in this field is used as the frames priority when bits [7:2] of the frames ip tos/diffserv/traffic class value is 0x 05 . 00 1-0 dscp[9:8] r/w the value in this field is used as the frames priority when bits [7:2] of the frames ip tos/diffserv/traffic class value is 0x 04 . 00 register 98 (0x62): tos priority control register 2 bit name r/w description default 7-6 dscp[23:22] r/w the value in this field is used as the frames priority when bits [7:2] of the frames ip tos/diffserv/traffic class value is 0x 0b . 00 5-4 dscp[21:20] r/w the value in this field is used as the frames priority when bits [7:2] of the frames ip tos/diffserv/traffic class value is 0x 0a . 00 3-2 dscp[19:18] r/w the value in this field is used as the frames priority when bits [7:2] of the frames ip tos/diffserv/traffic class value is 0x 09 . 00 1-0 dscp[17:16] r/w the value in this field is used as the frames priority when bits [7:2] of the frames ip tos/diffserv/traffic class value is 0x 08 . 00 downloaded from: http:/// micrel, inc. ksz8873mll/fll/rll september 20, 2013 74 revision 1.6 register 99 (0x63): tos priority control register 3 bit name r/w description default 7-6 dscp[31:30] r/w the value in this field is used as the frames priority when bits [7:2] of the frames ip tos/diffserv/traffic class value is 0x 0f . 00 5-4 dscp[29:28] r/w the value in this field is used as the frames priority when bits [7:2] of the frames ip tos/diffserv/traffic class value is 0x 0e . 00 3-2 dscp[27:26] r/w the value in this field is used as the frames priority when bits [7:2] of the frames ip tos/diffserv/traffic class value is 0x 0d . 00 1-0 dscp[25:24] r/w the value in this field is used as the frames priority when bits [7:2] of the frames ip tos/diffserv/traffic class value is 0x 0c . 00 register 100 (0x64): tos priority control register 4 bit name r/w description default 7-6 dscp[39:38] r/w the value in this field is used as the frames priority when bits [7:2] of the frames ip tos/diffserv/traffic class value is 0x 13 . 00 5-4 dscp[37:36] r/w the value in this field is used as the frames priority when bits [7:2] of the frames ip tos/diffserv/traffic class value is 0x 12 . 00 3-2 dscp[35:34] r/w the value in this field is used as the frames priority when bits [7:2] of the frames ip tos/diffserv/traffic class value is 0x 11 . 00 1-0 dscp[33:32] r/w the value in this field is used as the frames priority when bits [7:2] of the frames ip tos/diffserv/traffic class value is 0x 1 0. 00 register 101 (0x65): tos priority control register 5 bit name r/w description default 7-6 dscp[47:46] r/w the value in this field is used as the frames priority when bits [7:2] of the frames ip tos/diffserv/traffic class value is 0x 17 . 00 5-4 dscp[45:44] r/w the value in this field is used as the frames priority when bits [7:2] of the frames ip tos/diffserv/traffic class value is 0x 16 . 00 3-2 dscp[43:42] r/w the value in this field is used as the frames priority when bits [7:2] of the frames ip tos/diffserv/traffic class value is 0x 15 . 00 1-0 dscp[41:40] r/w the value in this field is used as the frames priority when bits [7:2] of the frames ip tos/diffserv/traffic class value is 0x 14 . 00 downloaded from: http:/// micrel, inc. ksz8873mll/fll/rll september 20, 2013 75 revision 1.6 register 102 (0x66): tos priority control register 6 bit name r/w description default 7-6 dscp[55:54] r/w the value in this field is used as the frames priority when bits [7:2] of the frames ip tos/diffserv/traffic class value is 0x 1b . 00 5-4 dscp[53:52] r/w the value in this field is used as the frames priority when bits [7:2] of the frames ip tos/diffserv/traffic class value is 0x 1a . 00 3-2 dscp[51:50] r/w the value in this field is used as the frames priority when bits [7:2] of the frames ip tos/diffserv/traffic class value is 0x 19 . 00 1-0 dscp[49:48] r/w the value in this field is used as the frames priority when bits [7:2] of the frames ip tos/diffserv/traffic class value is 0x 18 . 00 register 103 (0x67): tos priority control register 7 bit name r/w description default 7-6 dscp[63:62] r/w the value in this field is used as the frames priority when bits [7:2] of the frames ip tos/diffserv/traffic class value is 0x 1f . 00 5-4 dscp[61:60] r/w the value in this field is used as the frames priority when bits [7:2] of the frames ip tos/diffserv/traffic class value is 0x 1e . 00 3-2 dscp[59:58] r/w the value in this field is used as the frames priority when bits [7:2] of the frames ip tos/diffserv/traffic class value is 0x 1d . 00 1-0 dscp[57:56] r/w the value in this field is used as the frames priority when bits [7:2] of the frames ip tos/diffserv/traffic class value is 0x 1c . 00 register 104 (0x68): tos priority control register 8 bit name r/w description default 7-6 dscp[71:70] r/w the value in this field is used as the frames priority when bits [7:2] of the frames ip tos/diffserv/traffic class value is 0x 23 . 00 5-4 dscp[69:68] r/w the value in this field is used as the frames priority when bits [7:2] of the frames ip tos/diffserv/traffic class value is 0x 22 . 00 3-2 dscp[67:66] r/w the value in this field is used as the frames priority when bits [7:2] of the frames ip tos/diffserv/traffic class value is 0x 21 . 00 1-0 dscp[65:64] r/w the value in this field is used as the frames priority when bits [7:2] of the frames ip tos/diffserv/traffic class value is 0x 2 0. 00 downloaded from: http:/// micrel, inc. ksz8873mll/fll/rll september 20, 2013 76 revision 1.6 register 105 (0x69): tos priority control register 9 bit name r/w description default 7-6 dscp[79:78] r/w the value in this field is used as the frames priority when bits [7:2] of the frames ip tos/diffserv/traffic class value is 0x 27 . 00 5-4 dscp[77:76] r/w the value in this field is used as the frames priority when bits [7:2] of the frames ip tos/diffserv/traffic class value is 0x 26 . 00 3-2 dscp[75:74] r/w the value in this field is used as the frames priority when bits [7:2] of the frames ip tos/diffserv/traffic class value is 0x 25 . 00 1-0 dscp[73:72] r/w the value in this field is used as the frames priority when bits [7:2] of the frames ip tos/diffserv/traffic class value is 0x 24 . 00 register 106 (0x6a): tos priority control register 10 bit name r/w description default 7-6 dscp[87:86] r/w the value in this field is used as the frames priority when bits [7:2] of the frames ip tos/diffserv/traffic class value is 0x 2b . 00 5-4 dscp[85:84] r/w the value in this field is used as the frames priority when bits [7:2] of the frames ip tos/diffserv/traffic class value is 0x 2a . 00 3-2 dscp[83:82] r/w the value in this field is used as the frames priority when bits [7:2] of the frames ip tos/diffserv/traffic class value is 0x 29 . 00 1-0 dscp[81:80] r/w the value in this field is used as the frames priority when bits [7:2] of the frames ip tos/diffserv/traffic class value is 0x 28 . 00 register 107 (0x6b): tos priority control register 11 bit name r/w description default 7-6 dscp[95:94] r/w the value in this field is used as the frames priority when bits [7:2] of the frames ip tos/diffserv/traffic class value is 0x 2f . 00 5-4 dscp[93:92] r/w the value in this field is used as the frames priority when bits [7:2] of the frames ip tos/diffserv/traffic class value is 0x 2e . 00 3-2 dscp[91:90] r/w the value in this field is used as the frames priority when bits [7:2] of the frames ip tos/diffserv/traffic class value is 0x 2d . 00 1-0 dscp[89:88] r/w the value in this field is used as the frames priority when bits [7:2] of the frames ip tos/diffserv/traffic class value is 0x 2c . 00 downloaded from: http:/// micrel, inc. ksz8873mll/fll/rll september 20, 2013 77 revision 1.6 register 108 (0x6c): tos priority control register 12 bit name r/w description default 7-6 dscp[103:102] r/w the value in this field is used as the frames priority when bits [7:2] of the frames ip tos/diffserv/traffic class value is 0x 33 . 00 5-4 dscp[101:100] r/w the value in this field is used as the frames priority when bits [7:2] of the frames ip tos/diffserv/traffic class value is 0x 32 . 00 3-2 dscp[99:98] r/w the value in this field is used as the frames priority when bits [7:2] of the frames ip tos/diffserv/traffic class value is 0x 31 . 00 1-0 dscp[97:96] r/w the value in this field is used as the frames priority when bits [7:2] of the frames ip tos/diffserv/traffic class value is 0x 3 0. 00 register 109 (0x6d): tos priority control register 13 bit name r/w description default 7-6 dscp[111:110] r/w the value in this field is used as the frames priority when bits [7:2] of the frames ip tos/diffserv/traffic class value is 0x 37 . 00 5-4 dscp[109:108] r/w the value in this field is used as the frames priority when bits [7:2] of the frames ip tos/diffserv/traffic class value is 0x 36 . 00 3-2 dscp[107:106] r/w the value in this field is used as the frames priority when bits [7:2] of the frames ip tos/diffserv/traffic class value is 0x 35 . 00 1-0 dscp[105:104] r/w the value in this field is used as the frames priority when bits [7:2] of the frames ip tos/diffserv/traffic class value is 0x 34 . 00 register 110 (0x6e): tos priority control register 14 bit name r/w description default 7-6 dscp[119:118] r/w the value in this field is used as the frames priority when bits [7:2] of the frames ip tos/diffserv/traffic class value is 0x 3b . 00 5-4 dscp[117:116] r/w the value in this field is used as the frames priority when bits [7:2] of the frames ip tos/diffserv/traffic class value is 0x 3a . 00 3-2 dscp[115:114] r/w the value in this field is used as the frames priority when bits [7:2] of the frames ip tos/diffserv/traffic class value is 0x 39 . 00 1-0 dscp[113:112] r/w the value in this field is used as the frames priority when bits [7:2] of the frames ip tos/diffserv/traffic class value is 0x 38 . 00 downloaded from: http:/// micrel, inc. ksz8873mll/fll/rll september 20, 2013 78 revision 1.6 register 111 (0x6f): tos priority control register 15 bit name r/w description default 7-6 dscp[127:126] r/w the value in this field is used as the frames priority when bits [7:2] of the frames ip tos/diffserv/traffic class value is 0x 3f . 00 5-4 dscp[125:124] r/w the value in this field is used as the frames priority when bits [7:2] of the frames ip tos/diffserv/traffic class value is 0x 3e . 00 3-2 dscp[123:122] r/w the value in this field is used as the frames priority when bits [7:2] of the frames ip tos/diffserv/traffic class value is 0x 3d . 00 1-0 dscp[121:120] r/w the value in this field is used as the frames priority when bits [7:2] of the frames ip tos/diffserv/traffic class value is 0x 3c . 00 registers 112 to 117 registers 112 to 117 contain the switch engines mac address. this 48 - bit address is used as the source address for the macs full duplex flow control (pause) frame. register 112 (0x70): mac address register 0 bit name r/w description default 7-0 maca[47:40] r/w 0x00 register 113 (0x71): mac address register 1 bit name r/w description default 7-0 maca[39:32] r/w 0x10 register 114 (0x72): mac address register 2 bit name r/w description default 7-0 maca[31:24] r/w 0xa1 register 115 (0x73): mac address register 3 bit name r/w description default 7-0 maca[23:16] r/w 0xff register 116 (0x74): mac address register 4 bit name r/w description default 7-0 maca[15:8] r/w 0xff register 117 (0x75): mac address register 5 bit name r/w description default 7-0 maca[7:0] r/w 0xff downloaded from: http:/// micrel, inc. ksz8873mll/fll/rll september 20, 2013 79 revision 1.6 registers 118 to 120 registers 118 to 120 are user defined registers (udrs). these are general purpose read/write registers that can be used to pass user defined control and status information between the ksz88 73 and the external processor. register 118 (0x76): user defined register 1 bit name r/w description defa ult 7-0 udr1 r/w 0x00 register 119 (0x77): user defined register 2 bit name r/w description default 7-0 udr2 r/w 0x00 register 120 (0x78): user defined register 3 bit name r/w description default 7-0 udr3 r/w 0x00 registers 121 to 131 registers 121 to 131 provide read and write access to the static mac address table, vlan table, dynamic mac address table, and mib counters. register 121 (0x79): indirect access control 0 bit name r/w description default 7-5 reserved r/w reserved do not change the default values. 000 4 read high / write low r/w =1, read cycle =0, write cycle 0 3-2 table select r/w =00, static mac address table selected =01, vlan table selected =10, dynamic mac address table selected =11, mib counter selected 00 1-0 indirect address high r/w bits [9:8] of indirect address 00 register 122 (0x7a): indirect access control 1 bit name r/w description default 7-0 indirect address low r/w bits [7:0] of indirect address 0000_0000 note : a write to register 122 triggers the read/write command. read or write access is determ ined by register 121 bit 4. downloaded from: http:/// micrel, inc. ksz8873mll/fll/rll september 20, 2013 80 revision 1.6 register 123 (0x7b): indirect data register 8 bit name r/w description default 7 cpu read status ro this bit is applicable only for dynamic mac address table and mib counter reads. =1, read is still in progress =0, read has completed 0 6-3 reserved ro reserved 0000 2-0 indirect data [66:64] ro bits [66:64] of indirect data 000 register 124 (0x7c): indirect data register 7 bit name r/w description default 7-0 indirect data [63:56] r/w bits [63:56] of indirect data 0000_0000 register 125 (0x7d): indirect data register 6 bit name r/w description default 7-0 indirect data [55:48] r/w bits [55:48] of indirect data 0000_0000 register 126 (0x7e): indirect data register 5 bit name r/w description default 7-0 indirect data [47:40] r/w bits [47:40] of indirect data 0000_0000 register 127 (0x7f): indirect data register 4 bit name r/w description default 7-0 indirect data [39:32] r/w bits [39:32] of indirect data 0000_0000 register 128 (0x80): indirect data register 3 bit name r/w description default 7-0 indirect data [31:24] r/w bits [31:24] of indirect data 0000_0000 register 129 (0x81): indirect data register 2 bit name r/w description default 7-0 indirect data [23:16] r/w bits [23:16] of indirect data 0000_0000 downloaded from: http:/// micrel, inc. ksz8873mll/fll/rll september 20, 2013 81 revision 1.6 register 130 (0x82): indirect data register 1 bit name r/w description default 7-0 indirect data [15:8] r/w bits [15:8] of indirect data 0000_0000 register 131 (0x83): indirect data register 0 bit name r/w description default 7-0 indirect data [7:0] r/w bits [7:0] of indirect data 0000_0000 register 147~142(0x93~0x8e): station mac address 1 maca1 register 153~148 (0x99~0x94): station mac address 2 maca2 bit name r/w description default 47-0 station address r/w 48 - bit station address maca1 and maca2. note: this address is used for self mac address filtering, see the port register control 5 bits [6,5] for detail. 48h0 note: the msb bit[47 - 40] of the mac is the register 147 and 15 3 . the lsb bit[7 - 0] of mac is the register 142 and 148. register 154[6:0] (0x9a): port 1 q0 egre ss data rate l imit register 158[6:0] (0x9e): port 2 q0 egre ss data rate l imit register 162[6:0] (0xa2): port 3 q0 egre ss data rate l imit bit name r/w description default 7 egress rate limit flow control enable r/w =1, enable egress rate limit flow control. =0, disable 0 6-0 q0 egress data rate limit r/w egress data rate limit for priority 0 frames egress traffic from this priority queue is shaped according to the data rate limit table. 0 register 155[6:0] (0x9b): port 1 q1 egre ss data rate l imit register 159[6:0] (0x9f): port 2 q1 egre ss data rate l imit register 163[6:0] (0xa3): port 3 q1 egre ss data rate l imit bit name r/w description default 7 reserved r/w reserved do not change the default values. 0 6-0 q1 egress data rate limit r/w egress data rate limit for priority 1 frames egress traffic from this priority queue is shaped according to the data rate limit table. 0 downloaded from: http:/// micrel, inc. ksz8873mll/fll/rll september 20, 2013 82 revision 1.6 register 156[6:0] (0x9c): port 1 q2 egre ss data rate l imit register 160[6:0] (0xa0): port 2 q2 egre ss data rate l imit register 164[6:0] (0xa4): port 3 q2 egre ss data rate l imit bit name r/w description default 7 reserved r/w reserved do not change the default values. 0 6-0 q2 egress data rate limit r/w egress data rate limit for priority 2 frames egress traffic from this priority queue is shaped according to the data rate limit table. 0 register 157[6:0] (0x9d): port 1 q3 egress data rate l imit register 161[6:0] (0xa1): port 2 q3 egre ss data rate l imit register 165[6:0] (0xa5): port 3 q3 egre ss data rate l imit bit name r/w description default 7 reserved r/w reserved do not change the default values. 0 6-0 q3 egress data rate limit r/w egress data rate limit for priority 3 frames egress traffic from this priority queue is shaped according to the data rate limit table. 0 register 166 (0xa6): ksz8873 mode i ndicator bit name ro description default 7-0 ksz8873 mode indicator ro bit7: 1: 2 mii mode bit6: 1: 48p pkg of 2 phy mode bit5: 1: reserved 0: reserved bit4: 1: port 3 rmii 0: port 3 mii bit 3 : 1: reserved 0: reserved bit2: 1: port 3 mac mii 0: port 3 phy mii bit1: 1: port 1 copper 0: port 1 fibe r bit0: 1: port 2 copper 0: port 2 fiber 0x03 mll 0x13 rll 0x0 0 fll register 167 (0xa7): high - priority packet buffer reserved for q 3 bit name rw description default 7-0 reserved ro reserved do not change the default values. 0x45 register 168 (0xa8): high - priority packet buffer reserved for q 2 bit name rw description default 7-0 reserved ro reserved do not change the default values. 0x35 downloaded from: http:/// micrel, inc. ksz8873mll/fll/rll september 20, 2013 83 revision 1.6 register 169 (0xa9): high - priority packet buffer reserved for q 1 bit name rw description default 7-0 reserved ro reserved do not change the default values. 0x25 register 170 (0xaa): high - priority packet buffer reserved for q 0 bit name rw description default 7-0 reserved ro reserved do not change the default values. 0x15 register 171 (0xab): pm usage flow control select mode 1 bit name r/w description default 7 reserved ro reserved do not change the default values. 0 6 reserved ro reserved do not change the default values. 1 5-0 reserved ro reserved do not change the default values. 0x18 register 172 (0xac): pm usage flow control select mode 2 bit name r/w description default 7-6 reserved ro reserved do not change the default values. 0 5-0 reserved ro reserved do not change the default values. 0x10 register 173 (0xad): pm usage flow control select mode 3 bit name r/w description default 7-6 reserved ro reserved do not change the default values. 00 5-0 reserved ro reserved do not change the default values. 0x08 register 174 (0xae): pm usage flow control select mode 4 bit name r/w description default 7-4 reserved ro reserved do not change the default values. 0 3-0 reserved ro reserved do not change the default values. 0x05 downloaded from: http:/// micrel, inc. ksz8873mll/fll/rll september 20, 2013 84 revision 1.6 register 175 (0xaf): txq split for q 3 in port 1 bit name r/w description default 7 priority select r/w 0 = enable straight priority with reg 176/177/178 bits[7]=0 and reg 5 bit[3]=0 for higher priority first 1= priority ratio is 8:4:2:1 for 4 queues and 2:1 for 2 queues with reg 176/177/178 bits[7]=1 . 1 6:0 reserved ro reserved do not change the default values. 8 register 176 (0xb0): txq split for q 2 in port 1 bit name r/w description default 7 priority select r/w 0 = enable straight priority with reg 175/177/178 bits[7]=0 and reg 5 bit[3]=0 for higher priority first 1= priority ratio is 8:4:2:1 for 4 queues and 2:1 for 2 queues with reg 175/177/178 bits[7]=1 . 1 6:0 reserved ro reserved do not change the default values. 4 register 177 (0xb1): txq split for q 1 in port 1 bit name r/w description default 7 priority select r/w 0 = enable straight priority with reg 175/176/178 bits[7]=0 and reg 5 bit[3]=0 for higher priority first 1= priority ratio is 8:4:2:1 for 4 queues and 2:1 for 2 queues with reg 175/176/178 bits[7]=1 . 1 6:0 reserved ro reserved do not change the default values. 2 register 178 (0xb2): txq split for q 0 in port 1 bit name r/w description default 7 priority select r/w 0 = enable straight priority with reg 175/176/177 bits[7]=0 and reg 5 bit[3]=0 for higher priority first 1= priority ratio is 8:4:2:1 for 4 queues and 2:1 for 2 queues with reg 175/176/177 bits[7]=1 . 1 6:0 reserved ro reserved do not change the default values. 1 downloaded from: http:/// micrel, inc. ksz8873mll/fll/rll september 20, 2013 85 revision 1.6 register 179 (0xb3): txq split for q 3 in port 2 bit name r/w description default 7 priority select r/w 0 = enable straight priority with reg 1 80 /1 81 /1 82 bits[7]=0 and reg 5 bit[3]=0 for higher priority first 1= priority ratio is 8:4:2:1 for 4 queues and 2:1 for 2 queues with reg 1 80 /1 81 /1 82 bits[7]=1 . 1 6:0 reserved ro reserved do not change the default values. 8 register 180 (0xb4): txq split for q2 in port 2 bit name r/w description default 7 priority select r/w 0 = enable straight priority with reg 1 79 /1 81 /1 82 bits[7]=0 and reg 5 bit[3]=0 for higher priority first 1= priority ratio is 8:4:2:1 for 4 queues and 2:1 for 2 queues with reg 1 79 /1 81 /1 82 bits[7]=1 . 1 6:0 reserved ro reserved do not change the default values. 4 register 181 (0xb5): txq split for q 1 in port 2 bit name r/w description default 7 priority select r/w 0 = enable straight priority with reg 1 79 /1 80 /1 82 bits[7]=0 and reg 5 bit[3]=0 for higher priority first 1= priority ratio is 8:4:2:1 for 4 queues and 2:1 for 2 queues with reg 1 79 /1 80 /1 82 bits[7]=1 . 1 6:0 reserved ro reserved do not change the default values. 2 register 182 (0xb6): txq split for q 0 in port 2 bit name r/w description default 7 priority select r/w 0 = enable straight priority with reg 1 79 /1 80 /1 81 bits[7]=0 and reg 5 bit[3]=0 for higher priority first 1= priority ratio is 8:4:2:1 for 4 queues and 2:1 for 2 queues with reg 1 79 /1 80 /1 81 bits[7]=1 . 1 6:0 reserved ro reserved do not change the default values. 1 downloaded from: http:/// micrel, inc. ksz8873mll/fll/rll september 20, 2013 86 revision 1.6 register 183 (0xb7): txq split for q3 port 3 bit name r/w description default 7 priority select r/w 0 = enable straight priority with reg 1 84 /1 85 /1 86 bits[7]=0 and reg 5 bit[3]=0 for higher priority first 1= priority ratio is 8:4:2:1 for 4 queues and 2:1 for 2 queues with reg 1 84 /1 85 /1 86 bits[7]=1 . 1 6:0 reserved ro reserved do not change the default values. 8 register 184 (0xb8): txq split for q2 port 3 bit name r/w description default 7 priority select r/w 0 = enable straight priority with reg 1 83 /1 85 /1 86 bits[7]=0 and reg 5 bit[3]=0 for higher priority first 1= priority ratio is 8:4:2:1 for 4 queues and 2:1 for 2 queues with reg 1 83 /1 85 /1 86 bits[7]=1 . 1 6:0 reserved ro reserved do not change the default values. 4 register 185 (0xb9): txq split for q1 in port 3 bit name r/w description default 7 priority select r/w 0 = enable straight priority with reg 1 83 /1 84 /1 86 bits[7]=0 and reg 5 bit[3]=0 for higher priority first 1= priority ratio is 8:4:2:1 for 4 queues and 2:1 for 2 queues with reg 1 83 /1 84 /1 86 bits[7]=1 . 1 6:0 reserved ro reserved do not change the default values. 2 register 186 (0xba): txq split for q 0 in port 3 bit name r/w description default 7 priority select r/w 0 = enable straight priority with reg 1 83 /1 84 /1 85 bits[7]=0 and reg 5 bit[3]=0 for higher priority first 1= priority ratio is 8:4:2:1 for 4 queues and 2:1 for 2 queues with reg 1 83 /1 84 /1 85 bits[7]=1 . 1 6:0 reserved ro reserved do not change the default values. 1 register 187 (0xbb): interrupt enable r egister bit name r/w description default 7-0 interrupt enable register r/w interrupt enable register corresponding to bits in register 188 note: set register 187 first and then set register 188 (w1c= write 1 clear) to wait the interrupt at p in 35 intrn for the link to be changed. 0x00 downloaded from: http:/// micrel, inc. ksz8873mll/fll/rll september 20, 2013 87 revision 1.6 register 188 (0xbc): link change interrupt bit name r/w description default 7 p1 or p2 link change (lc) interrupt r/w set to 1 when p1 or p2 link changes in analog interface (w1c). 0 6-3 reserved r/w reserved do not change the default values. 0 2 p3 link change (lc) interrupt r/w set to 1 when p3 link changes in mii interface (w1c). 0 1 p2 link change (lc) interrupt r/w set to 1 when p2 link changes in analog interface (w1c). 0 0 p1 mii link change (lc) interrupt r/w set to 1 when p1 link changes in analog interface or mii interface (w1c). 0 register 189 (0xbd): force pause off iteration limit enable bit name r/w description default 7-0 force pause off iteration limit enable r/w =1, enable, it is 160ms before requesting to invalidate flow control. =0, disable 0 register 192 (0xc0): fiber signal threshold bit name r/w description default 7 port 2 fiber signal threshold r/w =1, threshold is 2.0v =0, threshold is 1.2v 0 6 port 1 fiber signal threshold r/w =1, threshold is 2.0v =0, threshold is 1.2v 0 5-0 reserved ro reserved do not change the default value. 0 register 19 3 (0xc 1 ): internal 1.8v ldo control bit name r/w description default 7 reserved ro reserved do not change the default value. 0 6 internal 1.8v ldo disable r/w =1, disable internal 1.8v ldo =0, enable internal 1.8v ldo 0 5-0 reserved ro reserved do not change the default value. 0 downloaded from: http:/// micrel, inc. ksz8873mll/fll/rll september 20, 2013 88 revision 1.6 register 194 (0xc2): insert src pvid bit name r/w description default 7-6 reserved ro reserved do not change the default value. 00 5 insert src port 1 pvid at port 2 r/w 1= insert src port 1 pvid for untagged frame at egress port 2 0 4 insert src port 1 pvid at port 3 r/w 1= insert src port 1 pvid for untagged frame at egress port 3 0 3 insert src port 2 pvid at port 1 r/w 1= insert src port 2 pvid for untagged frame at egress port 1 0 2 insert src port 2 pvid at port 3 r/w 1= insert src port 2 pvid for untagged frame at egress port 3 0 1 insert src port 3 pvid at port 1 r/w 1= insert src port 3 pvid for untagged frame at egress port 1 0 0 insert src port 3 pvid at port 2 r/w 1= insert src port 3 pvid for untagged frame at egress port 2 0 downloaded from: http:/// micrel, inc. ksz8873mll/fll/rll september 20, 2013 89 revision 1.6 register 195 (0xc3): power management and led mode bit name r/w description default 7 cpu i nterface power down r/w cpu interface clock tree power down enable. =1, enable =0, disable note: power save a little bit when mii interface is used and the traffic is stopped in the power management with normal mode 0 6 switch power down r/w switch clock tree power down enable. =1, enable =0, disable note: power save a little bit when mii interface is used and the traffic is stopped in the power management with normal mode 0 5-4 led mode selection r/w =00, led0 - > link/act, led1 - > speed =01 , led0 - > link, led1 - > act =10 , led0 - > link/act, led1 - > duplex =11, led0 - > link, led1 - > duplex note: item pin state led definition no link h off l ink l on 100 speed l on 10 speed h off (link is on) full duplex l on half duplex h off (link is on) act toggle blinking 00 3 led output m ode r/w =1, the internal stretched energy signal from the analog module will be negated and output to led1 and the internal device ready signal will be negated and output to led0. =0, the led1/led0 pins will indicate the regular led outputs. (note. this is for debugging purpose.) 0 2 pll off enable r/w =1, pll power down enable =0, disable note: this bit is used in energy detect mode with p in 27 mii_link_3 pull - up in the by - pass mode for saving power 0 1-0 power management mode r/w power management mode =00, normal mode =01, energy detection mode =10, s oft ware power d ow n mode =11, power saving mode 00 downloaded from: http:/// micrel, inc. ksz8873mll/fll/rll september 20, 2013 90 revision 1.6 register 196(0xc4): sleep mode bit name r/w description default 7-0 sleep mode r/w this value is used to control the minimum period the no energy event has to be detected consecutively before the device enters the low power state when the ed mode is on. the unit is 20ms. the default go sleep time is 1.6 seconds. 0x50 register 198 (0xc6): forward invalid vid frame and host mode bit name r/w description default 7 reserved ro reserved do not change the default value. 0 6-4 forward invid vid frame r/w forwarding ports for frame with invalid vid 3b0 3 p3 rmii clock selection r/w =1, internal =0, external 0 2 p1 rmii clock selection r/w =1, internal =0, external 0 1-0 host interface mode r/w =00, i 2 c master mode =01, i 2 c slave mode =10, spi slave mode =11, smi mode strapped value of p2led1, p2led0. downloaded from: http:/// micrel, inc. ksz8873mll/fll/rll september 20, 2013 91 revision 1.6 static mac address table the ksz8873 supports both a static and a dynamic mac address table. in respons e to a destination address (da) look up, the ksz8873 searches both tables to make a packet forwarding decision. in response to a source address ( sa) look up, only the dynamic table is searched for aging, migration and learning purposes. the static da look up result takes precedence over the dynamic da look up result. if there is a da match in both tables, the result from the static table is used. the entries in the static table will not be aged out by the ksz8873. the static table is accessed by an external processor via the smi, spi or i 2 c interfaces. the external processor performs all addition, modification and deletion of static mac table entries. table 16 . format of static mac t able (8 entries) bit name r/w description default 57 - 54 fid r/w filter vlan id C identifies one of the 16 active vlans 0000 53 use fid r/w =1, use (fid+mac) for static table look ups =0, use mac only for static table look ups 0 52 override r/w =1, override port setting transmit enable=0 or receive enable=0 setting =0, no override 0 51 valid r/w =1, this entry is valid, the lookup result will be used =0, this entry is not valid 0 50 - 48 forwarding ports r/w these 3 bits control the forwarding port(s): 001, forward to port 1 010, forward to port 2 100, forward to port 3 011, forward to port 1 and port 2 110, forward to port 2 and port 3 101, forward to port 1 and port 3 111, broadcasting (excluding the ingress port) 000 47 -0 mac addres s r/w 48 - bit mac address 0x0000_0000_0000 downloaded from: http:/// micrel, inc. ksz8873mll/fll/rll september 20, 2013 92 revision 1.6 examples : 1. static address table read (read the 2 nd entry) write to reg. 121 (0x79) with 0x10 // read static table selected write to reg. 122 (0x7a) with 0x01 // trigger the read operation then, read reg. 124 (0x7c), static table bits [57:56] read reg. 125 (0x7d), static table bits [55:48] read reg. 126 (0x7e), static table bits [47:40] read reg. 127 (0x7f), static table bits [39:32] read reg. 128 (0x80), static table bits [31:24] read reg. 129 (0x81), static table bits [23:16] read reg. 130 (0x82), static table bits [15:8] read reg. 131 (0x83), static table bits [7:0] 2. static address table write (write the 8 th entry) write to reg. 124 (0x7c), static table bits [57:56] write to reg. 125 (0x7d), static table bits [55:48] write to reg. 126 (0x7e), static table bits [47:40] write to reg. 127 (0x7f), static table bits [39:32] write to reg. 128 (0x80), static table bits [31:24] write to reg. 129 (0x81), static table bits [23:16] wr ite to reg. 130 (0x82), static table bits [15:8] write to reg. 131 (0x83), static table bits [7:0] write to reg. 121 (0x79) with 0x00 // write static table selected write to reg. 122 (0x7a) with 0x07 // trigger the write operation downloaded from: http:/// micrel, inc. ksz8873mll/fll/rll september 20, 2013 93 revision 1.6 vlan table the ksz8873 uses the vlan table to perform look ups. if 802.1q vlan mode is enabled (register 5, bi t 7 = 1), this table will be used to retrieve the vlan information that is associated with the i ngress packet. this information includes fid (filter id), vid ( vlan id), and vlan membership as described in table 17 . table 17 . format of static vlan table (16 entries) bit name r/w description default 19 valid r/w = 1, entry is valid = 0, entry is invalid 1 18 - 16 membership r/w specify which ports are members of the vlan. if a da lookup fails (no match in both static and dynamic tables), the packet associated with this vlan will be forwarded to ports specified in this field. for example, 101 means port 3 and 1 are in this vlan. 111 15 - 12 fid r/w filter id. ksz88 73 supports 16 active vlans represented by these four bit fields. fid is the mapped id. if 802.1q vlan is enabled, the look up will be based on fid+da and fid+sa. 0x0 11 -0 vid r/w ieee 802.1q 12 bits vlan id 0x001 if 802.1q vlan mode is enabled, ksz88 73 will assign a vid to every ingress packet. if the packet is untagged or tagged with a null vid, the packet is assigned with the default port vid of the ingress port. if the packet is tagged with non - null vid, the vid in the tag will be used. the look up process will start from the vlan tabl e look up. if the vid is not valid, the packet will be dropped and no address learning will take place. if the vi d is valid, the fid is retrieved. the fid+da and fid+sa lookups are performed. the fid+da look up determines the forwarding ports. if fid+da fails, the packet will be broadcast to all the members (excluding the ingress port) of the vlan. if fid+sa fails , the fid+sa will be learned. examples: 1. vlan table read (read the 3 rd e ntry) write to reg. 121 (0x79) with 0x14 // read vlan table selected write to reg. 122 (0x7a) with 0x02 // trigger the read operation then, read reg. 129 (0x81), vlan table bits [19:16] read reg. 130 (0x82), vlan table bits [15:8] read reg. 131 (0x83), vlan table bits [7:0] 2. vlan table write (write the 7 th entry) write to reg. 129 (0x81), vlan table bits [19:16] write to reg. 130 (0x82), vlan table bits [15:8] write to reg. 131 (0x83), vlan table bits [7:0] write to reg. 121 (0x79) with 0x04 // write vlan table selected write to reg. 122 (0x7a) with 0x06 // trigger the write operation downloaded from: http:/// micrel, inc. ksz8873mll/fll/rll september 20, 2013 94 revision 1.6 dynamic mac address table the ksz8873 maintains the dynamic mac address table. read access is allowed only. table 18 . format of dynamic mac address table (1k entries) bit name r/w description default 71 data not ready ro = 1, entry is not ready, continue retrying until this bit is set to 0 = 0, entry is ready 70 - 67 reserved ro reserved 66 mac empty ro = 1, there is no valid entry in the table = 0, there are valid entries in the table 1 65 - 56 no of valid entries ro indicates how many valid entries in the table 0x3ff means 1k entries 0x001 means 2 entries 0x000 and bit 66 = 0 means 1 entry 0x000 and bit 66 = 1 means 0 entry 00_0000_0000 55 - 54 time stamp ro 2 bits counter for internal aging 53 - 52 source port ro the source port where fid+mac is learned 00 : port 1 01 : port 2 10 : port 3 00 51 - 48 fid ro filter id 0x0 47 -0 mac address ro 48 - bit mac address 0x0000_0000_0000 example: 1. dynamic mac address table read (read the 1 st entry and retrieve the mac table size) write to reg. 121 (0x79) with 0x18 // read dynamic table selected write to reg. 122 (0x7a) with 0x00 // trigger the read operation then, read reg. 123 (0x7b), bit [7] // if bit 7 = 1, rest art (reread) from this register dynamic table bits [66:64] read reg. 124 (0x7c), dynamic table bits [63:56] read reg. 125 (0x7d), dynamic table bits [55:48] read reg. 126 (0x7e), dynamic table bits [47:40] read reg. 127 (0x7f), dynamic table bits [39:32] read reg. 128 (0x80), dynamic table bits [31:24] read reg. 129 (0x81), dynamic table bits [23:16] read reg. 130 (0x82), dynamic table bits [15:8] read reg. 131 (0x83), dynamic table bits [7:0] downloaded from: http:/// micrel, inc. ksz8873mll/fll/rll september 20, 2013 95 revision 1.6 management information base (mi b) counters the ksz8873 provides 34 mib counters per port. these counters are used to monitor the port activi ty for network management. the mib counters have two format groups: per port and all port dropped packet. table 19 . format of per port mi b counters bit name r/w description default 31 overflow ro = 1, counter overflow = 0, no counter overflow 0 30 count v alid ro = 1, counter value is valid = 0, counter value is not valid 0 29 -0 counter v alues ro counter value 0 per port mib counters are read using indirect memory access. the base address offsets and addres s ranges for all three ports are: port 1, base is 0x00 and range is (0x00 - 0x1f) port 2, base is 0x20 and range is (0x20 - 0x3f) port 3, base is 0x40 and range is (0x40 - 0x5f) port 1 mib counters are read using the indirect memory offsets in table 20 . downloaded from: http:/// micrel, inc. ksz8873mll/fll/rll september 20, 2013 96 revision 1.6 table 20 . port 1s per port mi b counters indirect memory offsets offset counter name description 0x0 rxloprioritybyte rx lo - priority (default) octet count including bad packets 0x1 rxhiprioritybyte rx hi - priority octet count including bad packets 0x2 rxundersizepkt rx undersize packets w/ good crc 0x3 rxfragments rx fragment packets w/ bad crc, symbol errors or alignment errors 0x4 rxoversize rx oversize packets w/ good crc (max: 1536 or 1522 bytes) 0x5 rxjabbers rx packets longer than 1522 bytes w/ either crc errors, alignment errors, or symbol error s (depends on max packet size setting) 0x6 rxsymbolerror rx packets w/ invalid data symbol and legal packet size. 0x7 rxcrcerror rx packets within (64,1522) bytes w/ an integral number of bytes and a bad crc (upper limit depends on max packet size setting) 0x8 rxalignmenterror rx packets within (64,1522) bytes w/ a non - integral number of bytes and a bad crc (upper limit depends on max packet size setting) 0x9 rxcontrol8808pkts number of mac control frames received by a port with 88 - 08h in ethertyp e field 0xa rxpausepkts number of pause frames received by a port. pause frame is qualified with etherty pe (88 - 08h), da, control opcode (00 - 01), data length (64b min), and a valid crc 0xb rxbroadcast rx good broadcast packets (not including error broadcast packets or valid multicast pa ckets) 0xc rxmulticast rx good multicast packets (not including mac control frames, error multicast packet s or valid broadcast packets) 0xd rxunicast rx good unicast packets 0xe rx64octets total rx packets (bad packets included) that were 64 octets in length 0xf rx65to127octets total rx packets (bad packets included) that are between 65 and 127 octets in length 0x10 rx128to255octets total rx packets (bad packets included) that are between 128 and 255 octets in length 0x11 rx256to511octets total rx packets (bad packets included) that are between 256 and 511 octets in length 0x12 rx512to1023octets total rx packets (bad packets included) that are between 512 and 1023 octets in length 0x13 rx1024to1522octets total rx packets (bad packets included) that are between 1024 and 1522 octets in length (upper limit depends on max packet size setting) 0x14 txloprioritybyte tx lo - priority good octet count, including pause packets 0x15 txhiprioritybyte tx hi - priority g ood octet count, including pause packets 0x16 txlatecollision the number of times a collision is detected later than 512 bit - times into the tx of a packet 0x17 txpausepkts number of pause frames transmitted by a port 0x18 txbroadcastpkts tx good broadcast packets (not including error broadcast or valid multicast packets) 0x19 txmulticastpkts tx good multicast packets (not including error multicast packets or valid broadcast packets) 0x1a txunicastpkts tx good unicast packets 0x1b txdeferred tx packets by a port for which the 1st tx attempt is delayed due to the busy medium 0x1c txtotalcollision tx total collision, half duplex only 0x1d txexcessivecollision a count of frames for which tx fails due to excessive collisions 0x1e txsinglecollision successfully tx frames on a port for which tx is inhibited by exactly one collision 0x1f txmultiplecollision successfully tx frames on a port for which tx is inhibited by more than one collision downloaded from: http:/// micrel, inc. ksz8873mll/fll/rll september 20, 2013 97 revision 1.6 table 21 . format of all port dropped packet mib counters bit name r/w description default 30 - 16 reserved n/a reserved n/a 15 -0 counter value ro counter value 0 all port dropped packet mib counters are read using indirect memory access. the address offsets for these counters are shown in table 22. table 22 . all port dropped packet mib counters offset counter name description 0x100 port1 tx drop packets tx packets dropped due to lack of resources 0x101 port2 tx drop packets tx packets dropped due to lack of resources 0x102 port3 tx drop packets tx packets dropped due to lack of resources 0x103 port1 rx drop packets rx packets dropped due to lack of resources 0x104 port2 rx drop packets rx packets dropped due to lack of resources 0x105 port3 rx drop packets rx packets dropped due to lack of resources examples: 1. mib counter read (read port 1 rx64octets counter) write to reg. 121 (0x79) with 0x1c // read mib counters selected write to reg. 122 (0x7a) with 0x0e // trigger the read operation then , read reg. 128 (0x80), overflow bit [31] // if bit 31 = 1, there was a counter overflow valid bit [30] // if bit 30 = 0, rest ar t (reread) from this register counter bits [29:24] read reg. 129 (0x81), counter bits [23:16] read reg. 130 (0x82), counter bits [15:8] read reg. 131 (0x83), counter bits [7:0] 2. mib counter read (read port 2 rx64octets counter) write to reg. 121 (0x79) with 0x1c // read mib counter selected write to reg. 122 (0x7a) with 0x2e // trigger the read operation then, read reg. 128 (0x80), overflow bit [31] // if bit 31 = 1, there was a counter overflow valid bit [30] // if bit 30 = 0, rest art (reread) from this register counter bits [29:24] read reg. 129 (0x81), counter bits [23:16] read reg. 130 (0x82), counter bits [15:8] read reg. 131 (0x83), counter bits [7:0] downloaded from: http:/// micrel, inc. ksz8873mll/fll/rll september 20, 2013 98 revision 1.6 3. mib counter read (read port1 tx drop packets counter) write to reg. 121 (0x79) with 0x1d // read mib counter selected write to reg. 122 (0x7a) with 0x00 // trigger the read operation then , read reg. 130 (0x82), counter bits [15:8] read reg. 131 (0x83), counter bits [7:0] additional mib counter information per port mib counters are designed as read clear. these counters will be cleared after they are read. all port dropped packet mib counters are not cleared after they are acc essed and do not indicate overflow or validity; therefore, the application must keep track of overflow and valid conditions. to read out all the counters, the best performance over the spi bus is (160+3)*8*200 = 260ms, where there are 160 registers, 3 overheads, 8 clocks per access, at 5mhz. in the heaviest condition, the counters will overflow in 2 minutes. it is recommended that the software read all the counters at least every 30 seconds. a high - performance spi master is also recommended to prevent counters overflow. downloaded from: http:/// micrel, inc. ksz8873mll/fll/rll september 20, 2013 99 revision 1.6 absolute maximum ratings ( 6 ) supply voltage v dda_1.8 , v ddc . ........................................ ? 0.5v to +2.4v v dda_3.3 , v ddio ......................................... ? 0.5v to +4.0v input voltage ................................................ ? 0.5v to +4.0v output voltage ............................................. ? 0.5v to +4.0v lead temperature (soldering, 10 s) ............................ 260 c storage temperature (t s) ......................... ? 55c to +150 c esd rating ( 8 ) ................................................................ 3 kv operating ratings ( 7 ) supply v oltage v dda_1.8 , v ddc ..................................... + 1.66 v to + 1.94 v v dda_3.3 ............................................... +2.5v to +3.465v v ddio ................................................. +1.71v to +3.465v ambient temperature (t a ) commercial ............................................... 0c to +70 c industrial ............................................... C 40c to +85c junction temperature (t j ) ....................................... +125 c junction thermal resistance ( 9 ) lqfp ( ja ) .................................................... 47.24 c/w lqfp ( jc ) .................................................... 19.37 c/w electrical characteristics ( 10 ) current consumption is for the single 3.3v supply device only, and includes the 1.8v supply voltages (v dda , v ddc ) that are provided via power output p in 56(v ddco ). each phy ports transformer consumes an additional 45ma @ 3.3v for 100base - tx and 70ma @ 3.3v for 10base -t at fully traffic . symbol parameter condition min . typ . max . units 100base - tx operation (all ports @ 100% utilization) i ddxio 100base- tx (analog core + digital core + transceiver + digital i/o) v dda_3.3 , v ddio = 3.3v core power is provided from the internal 1.8v ldo with input voltage v ddio 1 15 ma 10base - t operation (all ports @ 100% utilization) i ddxio 10base- t (analog core + digital core + transceiver + digital i/o) v dda_3.3 , v ddio = 3.3v core power is provided from the internal 1.8v ldo with input voltage v ddio 86 ma power management mode (with mii/rmii in d efault phy m ode) i dd3 power - saving mode v dda_3.3 , v ddio = 3.3v unplug port 1 and port 2 set register 195 b it[1,0] = [1,1] 96 ma i dd4 soft power - down mode v dda_3.3 , v ddio = 3.3v set register 195 b it[1,0] = [1,0] 5 ma i dd5 energy - detect mode v dda_3.3 , v ddio = 3.3v unplug port 1 and port 2 set register 195 b it[7,0] = 0x05 with p ort 3 phy mode and by - pass mode. 15 ma notes: 6. exceeding the absolute maximum ratings may damage the device. 7. the device is not guaranteed to function outside its operating ratings. 8. devices are esd sensitive. handling precautions are recommended. human body model, 1.5k in series with 100pf. 9. no heat spreader (hs) in this package. 10. t a = +25 c. specification for packaged product only. downloaded from: http:/// micrel, inc. ksz8873mll/fll/rll september 20, 2013 100 revision 1.6 electrical characteristics ( 10 ) (continued) current consumption is for the single 3.3v supply device only, and includes the 1.8v supply voltages (v dda , v ddc ) that are provided via power output p in 56(v ddco ). each phy ports transformer consumes an additional 45ma @ 3.3v for 100base - tx and 70ma @ 3.3v for 10base -t at fully traffic . symbol parameter condition min . typ . max . units cmos inputs (vdd_io = 3.3v/2.5v/1.8v) v ih input high voltage 2.0/ 1.8 /1.3 v v il input low voltage 0.8/0. 7 /0. 5 v i in input current v in = gnd ~ v dd_io ? 10 10 a cmos outputs (vdd_io = 3.3v/2.5v/1.8v) v oh output high voltage i oh = - 8ma 2.4/ 2.0 /1.5 v v ol output low voltage i ol = 8ma 0.4/0.4/0. 3 v |ioz| output tri - state leakage 10 a 100base - tx transmit ( measured differentially after 1:1 transformer ) v o peak differential output voltage 100? termination across differential output 0.95 1.05 v v imb output voltage imbalance 100? termination across differential output 2 % t r /t f rise/fall time 3 5 ns rise/fall time imbalance 0 0.5 ns duty cycle distortion 0.5 ns overshoot 5 % output jitter peak - to - peak 0.7 1.4 ns 10base - t receive v sq squelch threshold 5mhz square wave 400 mv 10base - t transmi t (measured differentially after 1:1 t ransformer) v p peak differential output voltage 100? termination across differential output 2.4 v output jitter peak - to - peak 1.4 11 ns downloaded from: http:/// micrel, inc. ksz8873mll/fll/rll september 20, 2013 101 revision 1.6 timing specifications eeprom timing figure 15 . eeprom interface input timing diagram figure 16 . eeprom interface output timing diagram table 23 . eeprom timing parameters symbols parameters min . typ . max . unit t cyc1 clock cycle 16384 ns t s1 setup time 20 ns t h1 hold time 20 ns t ov1 output valid 4096 4112 4128 ns downloaded from: http:/// micrel, inc. ksz8873mll/fll/rll september 20, 2013 102 revision 1.6 mii timing figure 17 . mac mode mii timing ? data received from mii figure 18 . mac mode mii timing ? data transmitted to mii table 24 . mac mode mii timing parameters symbol parameter 10base - t/100base - tx min . typ . max . units t cyc3 clock cycle 400/40 ns t s3 set- up time 4 ns t h3 hold time 2 ns t ov3 output valid 7 11 16 ns downloaded from: http:/// micrel, inc. ksz8873mll/fll/rll september 20, 2013 103 revision 1.6 mii timing (continued) figure 19 . phy mode mii timing ? data received from mii figure 20 . phy mode mii timing ? data transmitted to mii table 25 . phy mode mii timing parameters symbol parameter 10baset/100baset min . typ . max . units t cyc4 clock cycle 400/40 ns t s4 set- up time 10 ns t h4 hold time 0 ns t ov4 output valid 18 19 ns downloaded from: http:/// micrel, inc. ksz8873mll/fll/rll september 20, 2013 104 revision 1.6 rmii timing refclk tcyc mtxd [1:0] mtxen t 1 t 2 transmit timing figure 21 . rmii timing ? data received from rmii refclk tcyc t od mrxd [1:0] mrxdv receive timing figure 22 . rmii timing parameters table 26 . rmii timing parameters symbols parameters min . typ . max . unit t cyc clock c ycle 20 ns t 1 setup time 4 ns t 2 hold time 2 ns t od output delay 6 16 ns downloaded from: http:/// micrel, inc. ksz8873mll/fll/rll september 20, 2013 105 revision 1.6 i 2 c slave mode timing figure 23 . i 2 c input timing figure 24 . i 2 c start bit timing figure 25 . i 2 c stop bit timing figure 26 . i 2 c output timing downloaded from: http:/// micrel, inc. ksz8873mll/fll/rll september 20, 2013 106 revision 1.6 i 2 c slave mode timing (continued) table 27 . i 2 c timing parameters note: data is only allowed to change during scl low time except start and stop bits. symbols parameters min . typ . max . unit t cyc clock cycle 400 ns t s setup time 33 half - cycle ns t h hold time 0 ns t tbs start bit setup t ime 33 ns t tbh start bit hold t ime 33 ns t sbs stop bit setup time 2 ns t sbh stop bit hold t ime 33 ns t ov output valid 64 96 ns downloaded from: http:/// micrel, inc. ksz8873mll/fll/rll september 20, 2013 107 revision 1.6 spi timing figure 27 . spi input timing table 28 . spi input timing parameters symbols parameters min . max . units f c clock f requency 5 mhz t chsl spisn inactive hold t ime 90 ns t slch spisn active s etup t ime 90 ns t chsh spisn active o ld t ime 90 ns t shch spisn inactive s etup t ime 90 ns t shsl spisn d eselect t ime 100 ns t dvch dat a i nput s etup t ime 20 ns t chdx data i nput hold t ime 30 ns t clch clock r ise t ime 1 s t chcl clock f all t ime 1 s t dldh data input rise t ime 1 s t dhdl data input fall t ime 1 s downloaded from: http:/// micrel, inc. ksz8873mll/fll/rll september 20, 2013 108 revision 1.6 spi timing (continued) figure 28 . spi output timing table 29 . spi output timing parameters symbols parameters min . max . units f c clock f requency 5 mhz t clqx spiq hold t ime 0 0 ns t clqv clock low to spiq v alid 60 ns t ch clock high t ime 90 ns t cl clock low t ime 90 t qlqh spiq rise t ime 50 ns t qhql spiq fall t ime 50 ns t shqz spiq disable t ime 100 ns downloaded from: http:/// micrel, inc. ksz8873mll/fll/rll september 20, 2013 109 revision 1.6 auto - negotiation timing auto- negotiation - fast link pulse timing t pw tx +/ tx - clock pulse data pulse clock pulse t pw t ctd t ctc t flpw t btb tx +/ tx - data pulse flp burst flp burst figure 29 . auto - negotiation timing table 30 . auto - negotiation timing parameters symbols parameters min . typ . max . units t btb flp burst to flp burst 8 16 24 ms t flpw flp burst width 2 ms t pw clock/data pulse width 100 ns t ctd clock pulse to data pulse 55.5 64 69.5 s t ctc clock pulse to clock pulse 111 128 139 s number of clock/data pulse per burst 17 33 downloaded from: http:/// micrel, inc. ksz8873mll/fll/rll september 20, 2013 110 revision 1.6 mdc/mdio timing figure 30 . mdc/mdio timing table 31 . mdc/mdio timing parameters timing parameter description min . typ . max . unit t p mdc period 400 ns t 1 md1 mdio (phy input) setup to rising edge of mdc 10 ns t md2 mdio (phy input) hold from rising edge of mdc 4 ns t md3 mdio (phy output) delay from rising edge of mdc 222 ns downloaded from: http:/// micrel, inc. ksz8873mll/fll/rll september 20, 2013 111 revision 1.6 reset timing the ksz8873mll/fll/rll reset timing requirement is summarized in figure 31 and table 32 . figure 31 . reset timing table 32 . reset timing parameters symbols parameters min . max . units t sr stable supply voltages to reset high 10 ms t cs configuration s etup t ime 50 ns t oh configuration hold t ime 50 ns t rc reset to strap - in pin o utput 50 s t vr 3.3v rise t ime 100 s note: after the de - assertion of reset, it is recommended to wait a minimum of 100 s before starting programming on the ma naged interface (i 2 c slave, spi slave, smi, miim). downloaded from: http:/// micrel, inc. ksz8873mll/fll/rll september 20, 2013 112 revision 1.6 reset circuit the reset circuit in figure 32 is recommended for powering up the ksz8873mll/fll/rll if reset is triggered only by the power supply. figure 32 . recommended reset circuit the reset circuit in figure 33 is recommended for applications where reset is driven by another device (e.g., cpu, fpga, etc),. at power - on - reset, r, c and d1 provide the necessary ramp rise time to reset the k sz8873mll/fll/rll device. the rst_out_n from cpu/fpga provides the warm reset after power - up. figure 33 . recommended reset circuit for interfacing with cpu/fpga reset output downloaded from: http:/// micrel, inc. ksz8873mll/fll/rll september 20, 2013 113 revision 1.6 selection of isolation transformers a 1:1 isolation transformer is required at the line interface. an isolatio n transformer with integrated common - mode choke is recommended for exceeding fcc requirements. table 33 gives recommended transformer characteristics. table 33 . tr ansformer selection criteria parameter value test condition turns r atio 1 ct : 1 ct open - circuit inductance (minimum ) 350 h 100mv, 100khz, 8ma leakage inductance (maximum ) 0.4 h 1mhz ( minimum ) inter - winding c apacitance ( maximum ) 12pf d.c. r esistance ( maximum ) 0.9 ? insertion l oss ( maximum ) 1.0db 0mhz C 65mhz hipot ( minimum ) 1500vrms table 34 . qualified single - port magnetics magnetic manufacturer part number auto mdi -x number of port bel fuse s558 - 5999 - u7 yes 1 bel fuse (magjack) si- 46001 yes 1 bel fuse (magjack) si- 50170 yes 1 delta lf8505 yes 1 lankom lf - h41s yes 1 pulse h1102 yes 1 pulse (low cost) h1260 yes 1 datatronic nt79075 yes 1 transpower hb726 yes 1 ycl lf - h41s yes 1 tdk (mag jack) tla - 6t718 yes 1 selection of reference crystal table 35 . typical reference crystal characteristics chacteristics value units frequency 25.00000 mhz frequency tolerance (maximum ) 50 ppm load capacitance ( maximum ) 20 pf series r esistance 40 ? downloaded from: http:/// micrel, inc. ksz8873mll/fll/rll september 20, 2013 114 revision 1.6 package information ( 11 ) and recommended landing pattern 64 -pin lqfp package note: 11. package information is correct as of the publication date. for updates and most current inf ormation, go to www.micrel.com . downloaded from: http:/// micrel, inc. ksz8873mll/fll/rll september 20, 2013 115 revision 1.6 micrel, inc. 2180 fortune drive san jose, ca 95131 usa tel +1 (408) 944 - 0800 fax +1 (408) 474 - 1000 web http://www.micrel.com micrel makes no representations or warranties with respect to the accuracy or comp leteness of the information furnished in this data sheet. this information is not intended as a warranty and micrel does not assume responsibility for its us e. micrel reserves the right to change circuitry, specifications and descriptions at any time without notice. no license, whether express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in micrels terms and conditions of sale for such products, mic rel assumes no liability whatsoever, and micrel disclaims any express or implied warranty relating to the sale and/ or use of micrel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any pat ent, copyright or other intellectual property right . micrel products are not designed or authorized for use as components in life support appl iances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. life support devices or systems are devic es or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to res ult in a significant injury to the user. a purchasers use or sale of micrel products for use in life support appliances, devices or systems is a purchasers own risk and purchaser agrees to fully indemnify micrel for any damages resulting from such use or sale. ? 20 11 micrel, incorporated. downloaded from: http:/// |
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